GOA Clock Input Transistor Sizing for 8K Display Voltage Drop
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Solution Overview
Problem
8K ultra-high resolution electronic devices face issues due to impedance differences between clock signal lines and Gate on Array (GOA) circuits, leading to variations in output signals, which affect display performance.
Innovation Solution
The display panel incorporates a configuration where each GOA unit has a pull-up module with a clock input transistor connected to clock signal lines, with varying transistor sizes and resistivity to compensate for voltage drop differences, ensuring consistent voltage drops across all GOA units and the clock driving chip.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If GOA circuits and thick copper design are adopted for 8K ultra-high resolution electronic devices, then the device can support high resolution display, but the impedance difference between clock signal lines and GOA circuits increases significantly
Solution Approach 1:
The patent applies local quality by differentiating the transistor structures in different GOA units based on their position. Specifically, GOA units are divided into first GOA units and second GOA units, with the first having transistors with larger channel width and/or longer channel length to compensate for greater voltage drops in clock signal lines, while the second has transistors with smaller channel width and/or shorter channel length. This localized adjustment of transistor parameters compensates for the impedance differences caused by the thick copper design and high resolution requirements.
2Adaptability or versatility
If the number of clock signal lines is increased to support more GOA units, then the coverage of clock signals is improved, but the voltage drop difference between different clock signal lines increases
Solution Approach 1:
The patent implements local quality by creating different transistor configurations for GOA units connected to different clock signal lines. The first GOA units connected to certain clock signal lines use transistors with larger channel width and/or longer channel length to compensate for greater voltage drops, while the second GOA units use transistors with smaller channel width and/or shorter channel length. This localized differentiation ensures that despite the increased number of clock signal lines for broader coverage, the voltage drop consistency across all GOA units is maintained.
Data Source
AI summary
A display panel and an electronic device is provided. A voltage drop value of the clock input transistor of a pull-up module of m1st GOA unit connected to an n1st clock signal line is greater than a voltage drop value of the clock input transistor of a pull-up module of m2nd GOA unit connected to the n2nd clock signal line. Based on this circuit structure, a CK impedance difference existing in 8K ultra-high resolution electronic devices can be alleviated.