GOI Chip Structure via SGOI Segmentation and Ge Condensation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The existing methods for preparing germanium-on-insulator (GOI) chip structures face challenges due to high dislocation density and complex techniques, which affect the quality and performance of the final device.
Innovation Solution
A method involving the SMART CUT technique to create a silicon-on-insulator (SGOI) structure, followed by germanium condensation technology to form a stacked structure with a second Si substrate, insulating buried layer, Ge layer, and SiO2 layer, and then etching off the SiO2 layer to obtain a GOI structure, utilizing ion implantation and high-temperature annealing to reduce threading dislocation density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If epitaxial SiGe is used on SOI substrate, then GOI structure can be formed, but high dislocation density (≥10^7) is introduced
Solution Approach 1:
The patent segments the GOI formation process into two distinct stages: first forming an SGOI structure with low dislocation density, then performing germanium condensation to achieve the final GOI structure. This segmentation allows each stage to be optimized independently, preventing the accumulation of high dislocation density throughout the entire process.
Solution Approach 2:
The patent performs preliminary formation of the SGOI structure with a thin germanium layer before the final germanium condensation step. This preliminary action establishes a low-dislocation foundation that prevents the propagation of misfit dislocations during subsequent processing, thereby maintaining high material quality.
2Manufacturing precision
If germanium condensation technology is applied, then GOI structure is formed, but the technique becomes complex
Solution Approach 1:
The patent merges the formation of the insulating buried layer and the germanium layer into a single germanium condensation process step. By combining these operations, the patent reduces the total number of process steps while achieving the desired GOI structure, thereby simplifying the overall technique.
Solution Approach 2:
The germanium condensation process serves multiple functions simultaneously: it forms the germanium layer, creates the insulating buried layer, and establishes the SGOI structure. This multi-functionality reduces the need for separate dedicated process steps, simplifying the overall preparation technique.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach simplifies the preparation of high-quality GOI chip structures by reducing misfit dislocations, enhancing the germanium condensation technology, and improving the possibility of wide use in the semiconductor industry.
Implementation Method 1
a SiGe layer... performing germanium condensation technology on the SGOI structure, so as to form a stacked structure, sequentially comprising a second Si substrate, an insulating buried layer BOX, a Ge layer, and a SiO2 layer
Implementation Method 2
performing H+ ion implantation on a surface of the SiGe layer by using an ion implantation technique, and controlling ion implanting energy to form one silicon layer rich in H+ ions as a cutting layer
Implementation Method 3
performing high-temperature annealing treatment on the bonded structure, so as to cut off a part of the first Si substrate from the cutting layer
Data Source
AI summary
The present invention provides a method for preparing a GOI chip structure, where, in the method, first, a SiGe on insulator (SGOI) chip structure is made by using a SMART CUT technology, and then, germanium condensation technology is performed on the SGOI chip structure, so as to obtain a GOI chip structure. Because the SGOI made by the Smart-Cut technology basically has no misfit dislocation in an SGOI/BOX interface, the threading dislocation density of the GOI is finally reduced. A technique of the present invention is simple, the high-quality GOI chip structure can be implemented, and the germanium condensation technology is greatly improved. An ion implantation technology and an annealing technology are quite mature techniques in the current semiconductor industry, so that such a preparation method greatly improves the possibility of wide use of the germanium concentration technology in the semiconductor industry.