Golay Sequence Circuit for 60 GHz Frame Timing Detection

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Solution Overview

Problem

The IEEE 802.15.3c Draft Standard's PHY preamble structure for wireless communication systems in the 60 GHz band faces challenges with low sensitivity in frame timing detection, particularly at low signal-to-noise (SNR) levels, due to its inability to effectively adapt channel estimation and poor accuracy in noncoherent methods.

Innovation Solution

A circuit and method using complementary Golay sequences and correlators are implemented to generate and process signals with specific delays and weight factors, enabling improved frame timing detection by outputting complementary Golay sequences or correlation signals, which facilitate more accurate synchronization and channel estimation.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If noncoherent frame timing detection method is used, then device complexity is reduced, but measurement precision (frame timing detection accuracy) deteriorates at low SNR levels

Engineering Contradiction:
Improveframe timing detection complexityVSAvoidframe timing detection accuracy
Core Design Contradiction:
Device complexityVSMeasurement precision

Solution Approach 1:

The patent introduces channel estimation as an intermediary mechanism between the received signal and frame timing detection. By estimating the channel characteristics using training sequences and applying these estimates to adjust the correlation calculations, the system achieves coherent detection performance without requiring complex coherent processing algorithms, thus resolving the contradiction between complexity and precision.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Measurement precision

If channel estimation adaptation is implemented, then measurement precision (channel estimation accuracy) is improved, but device complexity and processing time increase

Engineering Contradiction:
Improvechannel estimation accuracyVSAvoidprocessing complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent performs channel estimation using dedicated training sequences (SYNC and SFD fields) before the actual data transmission begins. This preliminary action allows the receiver to have accurate channel information ready for the upcoming data detection, improving measurement precision without adding complexity to the main data processing path.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent divides the preamble into distinct functional segments: SYNC field for initial synchronization and coarse channel estimation, SFD field for precise frame timing detection, and CES field for fine channel estimation. This segmentation allows each segment to perform its specific function efficiently, improving overall channel estimation accuracy while keeping processing complexity manageable through specialized processing paths.

Inventive Principle:
Principle #1Segmentation

3Measurement precision

If preamble length is increased to improve channel estimation, then measurement precision is improved, but loss of time increases

Engineering Contradiction:
Improvechannel estimation accuracyVSAvoidpreamble transmission time
Core Design Contradiction:
Measurement precisionVSLoss of time

Solution Approach 1:

The patent applies different quality levels to different parts of the preamble. The SYNC field uses a longer sequence for robust initial synchronization and coarse channel estimation in noisy environments. The SFD field uses a shorter, more power-efficient sequence for precise frame timing detection. The CES field provides additional channel estimation when needed. This local differentiation of quality allows accurate channel estimation without uniformly increasing the entire preamble length.

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS8989287B2Apparatus for generating spreading sequences and determining correlation
Publication Date: 2015.03.24 NXP USA INC
  • US8989287B2 patent drawing
  • US8989287B2 patent drawing
  • US8989287B2 patent drawing

AI summary

A circuit for use in a complementary Golay sequence generator or in a complementary Golay sequence correlator includes an input configured to receive an input signal, a set of delay elements, including delay elements corresponding to respective delays of 1, 2, 4, 8, 16, 32, and 64, and a set of multipliers interconnected with the input and the set of delay elements. The set of multipliers is configured to apply weight factors, and the weight factors define the sequence 1,1,−1,1,−1,1,−1. The circuit also includes a pair of outputs configured to output, in response to the input signal, one of (i) a pair of complementary Golay sequences or (ii) a pair of correlation output signals, using (a) the set of delay elements and (b) the set of weight multipliers.