GPGPU Local Memory Buffers for Pipeline Data Transfer
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Solution Overview
Problem
Conventional GPGPUs are limited in processing pipeline-based applications due to their highly parallel architecture, which prevents efficient data transfer and synchronization between processing stages, leading to increased memory bandwidth usage and inefficiencies in 2D and 3D graphics processing.
Innovation Solution
The extension of GPGPU architecture with local memory buffers connected between parallel processing units allows for direct, on-chip data transfer, transforming parallel processing units into pipeline stages and reducing memory bandwidth usage by eliminating the need for data retrieval and storage from external memory.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If GPGPU uses highly parallel processing units, then processing power for parallel applications is improved, but ability to implement pipeline-based computations deteriorates
Solution Approach 1:
The processing units are made dynamically reconfigurable, allowing them to switch between parallel processing mode and pipeline stage mode. This dynamic reconfiguration enables the same hardware to adapt to different computational paradigms, resolving the contradiction between optimized parallel processing and pipeline implementation capability
2Productivity
If GPGPU architecture is highly parallelized, then parallel processing efficiency is improved, but data transfer efficiency between processing stages deteriorates
Solution Approach 1:
Buffer memory is introduced as an intermediary component between processing units when operating in pipeline mode. This buffer enables efficient data transfer between pipeline stages by providing local storage, eliminating the need for continuous external memory access and thus maintaining high data transfer speed while supporting pipeline architecture
3Quantity of substance
If parallel processing units exchange data with external memory, then data availability is improved, but memory bandwidth usage increases
Solution Approach 1:
The memory system is segmented into local buffer memory associated with each processing unit and external system memory. When operating in pipeline mode, processing units utilize the local buffer memory for inter-stage data transfer, thereby segmenting the memory access pattern and reducing the burden on external memory bandwidth while maintaining data availability
Data Source
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AI summary
This disclosure describes techniques for extending the architecture of a general purpose graphics processing unit (GPGPU) with parallel processing units to allow efficient processing of pipeline-based applications. The techniques include configuring local memory buffers connected to parallel processing units operating as stages of a processing pipeline to hold data for transfer between the parallel processing units. The local memory buffers allow on-chip, low-power, direct data transfer between the parallel processing units. The local memory buffers may include hardware-based data flow control mechanisms to enable transfer of data between the parallel processing units. In this way, data may be passed directly from one parallel processing unit to the next parallel processing unit in the processing pipeline via the local memory buffers, in effect transforming the parallel processing units into a series of pipeline stages.