Shared GPIO Output Buffer Circuit for Low Leakage and Smaller Area
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing GPIO output buffer circuits face issues with leakage and increased area size due to separate level shifters and pre-driver pairs required for p-channel and n-channel field effect transistor drivers.
Innovation Solution
A GPIO output buffer circuit design that uses a single level shifter and pre-driver for both p-channel and n-channel drivers, incorporating delay circuits to adjust the duty cycle, resulting in a smaller area and lower leakage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If separate level shifters and pre-driver pairs are used for PFET and NFET drivers, then the output buffer can drive both p-channel and n-channel transistors, but the circuit area increases and leakage current increases
Solution Approach 1:
The patent implements a universal level shifter and pre-driver circuit that serves both PFET and NFET drivers through shared circuitry. The level shifter uses a single configuration of transistors and resistors that can generate appropriate gate voltages for both p-channel and n-channel devices, eliminating the need for separate dedicated circuits for each transistor type.
Solution Approach 2:
The patent merges previously separate level shifter and pre-driver circuits into a combined architecture where the same circuit blocks serve dual purposes. The level shifter output feeds into a shared pre-driver stage that can drive both PFET and NFET, reducing the total component count and circuit footprint while maintaining full functionality.
2Adaptability or versatility
If separate level shifters and pre-driver pairs are used for PFET and NFET drivers, then the output buffer can drive both p-channel and n-channel transistors, but the leakage current increases
Solution Approach 1:
The universal level shifter and pre-driver design reduces the total number of active devices and interconnections required to drive both PFET and NFET. By sharing circuit resources, the patent minimizes the cumulative leakage current that would otherwise accumulate across multiple separate circuits, while still providing full drive capability for both transistor types.
3Ease of operation
If delay circuits are added to adjust duty cycle, then the output buffer can control pulse width and timing, but the circuit area increases
Solution Approach 1:
The patent incorporates delay circuits within the pre-driver stage that perform duty cycle adjustment before the final driver stage. This preliminary timing control is integrated into the existing signal path, allowing duty cycle modification without requiring separate external delay circuits or additional signal processing stages that would increase overall circuit area.
Data Source
AI summary
The present disclosure relates to a structure including a level shifter circuit which receives an input signal and at least one voltage reference signal and outputs at least one level shifted output signal, a pre-driver circuit which receives the at least one level shifted output signal and outputs at least one pre-driver output signal, the pre-driver circuit including at least one delay circuit, and a main driver circuit which receives the at least one pre-driver output signal and outputs a main driver output signal.