Autonomous GPIO Buffer Control to Prevent Pad Contention

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Solution Overview

Problem

The existing GPIO programming flow for integrated circuits (ICs) is time-consuming and error-prone, leading to electrical pad contention and increased leakage current, especially during standby states, which affects battery life and debugging in portable devices.

Innovation Solution

A hardware-based finite state machine (FSM) integrated into an I/O controller autonomously configures GPIO pads based on architectural states, using weakpull impedance devices to prevent pad contention and adapt to different use cases, eliminating the need for intensive manual programming.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If manual GPIO programming is used, then configuration flexibility is maintained, but programming time increases and errors occur leading to pad contention

Engineering Contradiction:
Improvepad configuration correctnessVSAvoidprogramming time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The I/O controller autonomously determines its own operational mode (input/output) and configures pad directions without external intervention. The controller self-detects architectural states and automatically programs GPIO pads, eliminating manual programming errors and reducing configuration time while maintaining reliability.

Inventive Principle:
Principle #25Self-service

Solution Approach 2:

The system pre-configures pad directions based on predicted architectural states before actual operation begins. By anticipating future states and pre-programming appropriate pad configurations, the system avoids contention errors and reduces the time required for manual programming adjustments.

Inventive Principle:
Principle #10Preliminary action

2Loss of energy

If manual GPIO programming is used, then configuration accuracy can be controlled, but leakage current increases due to pad contention

Engineering Contradiction:
Improveleakage currentVSAvoidconfiguration complexity
Core Design Contradiction:
Loss of energyVSEase of operation

Solution Approach 1:

The I/O controller autonomously monitors architectural states and dynamically adjusts pad directions to prevent contention. This self-managing approach eliminates the need for complex manual configuration while preventing pad contention that would increase leakage current, thereby reducing energy loss without complicating operation.

Inventive Principle:
Principle #25Self-service

Solution Approach 2:

The system continuously monitors architectural states and uses this feedback to dynamically adjust pad configurations. This closed-loop control ensures pads are always correctly configured according to current operational needs, preventing contention-induced leakage while maintaining ease of operation through automatic adaptation.

Inventive Principle:
Principle #23Feedback

3Reliability

If autonomous buffer control is implemented, then pad contention is prevented, but device complexity increases

Engineering Contradiction:
Improvepad contention preventionVSAvoidcontrol logic complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The I/O controller performs multiple functions including autonomous mode determination, pad direction configuration, and contention prevention using a single integrated control logic. This multi-functional approach prevents pad contention while avoiding the need for separate dedicated circuits for each function, thereby limiting the increase in device complexity.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The patent combines autonomous control logic directly within the I/O controller, merging the functions of state detection, mode determination, and pad configuration into a single unified component. This integration prevents pad contention through coordinated control while minimizing the increase in overall device complexity by eliminating the need for separate control modules.

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentEP3075118B1Autonomously controlling a buffer of a processor
Publication Date: 2019.11.20 INTEL CORP
  • EP3075118B1 patent drawingFigure 1
  • EP3075118B1 patent drawingFigure 2
  • EP3075118B1 patent drawingFigure 3

AI summary

In an embodiment, an apparatus includes an input/output (I/O) buffer to couple a logic unit to another device coupled via a pad, and a logic coupled to the I/O buffer to detect a value on the pad and to control the I/O buffer to provide the value to the pad, responsive to entry into an architectural state. Other embodiments are described and claimed.