GPIO-Connected Chip Mounting Surface for Capacitive Authentication
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Solution Overview
Problem
Existing solutions for protecting against the use of cloned products, such as ink cartridges and toner cartridges, in printers are costly and require additional sensors to analyze special coatings, increasing manufacturing expenses.
Innovation Solution
A chip system that creates a measurable characteristic by repurposing a metal surface typically used as a ground contact to connect with a general-purpose input/output port, forming a virtual capacitor, which can be measured to verify authenticity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If special coatings are used for authentication, then authentication capability is improved, but manufacturing cost increases due to additional sensors required
Solution Approach 1:
The patent repurposes the existing metal surface, originally designed solely as a ground contact, to serve dual functions: maintaining its electrical grounding role while simultaneously acting as an authentication element through its capacitive properties. This eliminates the need for separate authentication components and sensors, reducing manufacturing costs while preserving authentication capability.
Solution Approach 2:
The metal surface itself provides the authentication characteristic through its inherent capacitive properties when connected to the GPIO port, without requiring external sensors or additional components. The existing structure serves its own authentication function, eliminating the need for separate detection mechanisms.
2Measurement precision
If additional sensors are added to analyze special coatings, then authentication accuracy is improved, but device complexity increases
Solution Approach 1:
The existing metal surface and GPIO port combination is repurposed to perform both grounding and authentication functions. The general-purpose input/output port, already present in the chip design, is utilized for capacitive measurement, eliminating the need for dedicated authentication sensors and reducing device complexity.
Solution Approach 2:
The patent uses the inherent capacitive coupling between the metal surface and surrounding structures as an intermediary mechanism for authentication. Instead of adding sensors to directly measure coating properties, the system measures the capacitive effect created by the metal surface configuration, which indirectly provides authentication information with simpler hardware.
3Ease of manufacture
If a virtual capacitor is formed using existing metal surfaces, then cost is reduced by avoiding additional sensors, but measurement precision may be affected
Solution Approach 1:
The patent focuses the authentication measurement on the specific local characteristics of the metal surface configuration and its capacitive coupling. By measuring the capacitive effect at this specific location through the GPIO port, the system achieves accurate authentication while using existing structures, maintaining both cost-effectiveness and measurement precision.
Solution Approach 2:
The system measures changes in capacitive parameters (capacitance value, charging/discharging time constants) of the virtual capacitor formed by the metal surface. By monitoring these electrical parameter variations, the system achieves precise authentication measurements using the repurposed existing structures without additional sensors.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution allows for the cost-effective authentication of chips by measuring a capacitance that is difficult to replicate, thereby protecting against the use of cloned products without the need for additional sensors.
Implementation Method 1
connecting the one or more metal surfaces not to a ground contact of the die, but rather to a general-purpose input/output port of the die. This forms a virtual capacitor.
Data Source
AI summary
A chip configured to be mounted on a carrier. The chip includes a die having an input/output circuit and a general-purpose input/output port, wherein the general-purpose input/output port is electrically conductively connected to the input/output circuit of the die. The chip further includes a package in which the die is at least partially embedded, and at least one metal surface on a mounting side of the chip, wherein the mounting side faces the carrier during mounting, wherein a size of the at least one metal surface is at least 10% of a size of the mounting side, and wherein the general-purpose input/output port is furthermore electrically conductively connected to the at least one metal surface.