GPIO Core Unlocking Device for CPU Systems

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Solution Overview

Problem

The existing methods for unlocking CPU cores in computer systems require purchasing specific north and south bridge chips from the same manufacturer, leading to increased costs and limited flexibility.

Innovation Solution

A computer system that uses GPIO ports of an embedded controller or south bridge chip to generate and transmit a combination of core unlocking signals directly to the CPU, allowing for core unlocking without the need for specific bridge chip specifications, thereby reducing costs and enhancing flexibility.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If the ACC function is executed by the south bridge chip to unlock CPU cores, then the CPU operating efficiency is improved, but the system cost increases due to requiring specific bridge chip series

Engineering Contradiction:
ImproveCPU operating efficiencyVSAvoidsystem cost
Core Design Contradiction:
ProductivityVSEase of manufacture

Solution Approach 1:

The core unlocking function is extracted from the south bridge chip and relocated to a standalone GPIO control device. This allows the unlocking capability to be separated from the expensive bridge chip series requirement, enabling use with generic or lower-cost bridge chips while maintaining the core unlocking functionality.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

A GPIO control device is introduced as an intermediary component between the BIOS/south bridge and the CPU. This mediator generates and transmits the core unlocking signals, replacing the need for the south bridge chip to directly perform the unlocking function, thereby decoupling the cost constraint from the functionality.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If the same series of north bridge chip and south bridge chip from the same company are used, then the core unlocking function is achieved, but the manufacturer flexibility is reduced

Engineering Contradiction:
Improvecore unlocking functionVSAvoidmanufacturer flexibility
Core Design Contradiction:
ReliabilityVSAdaptability or versatility

Solution Approach 1:

The GPIO control device is designed with universal compatibility across different bridge chip series and manufacturers. It can generate and transmit core unlocking signals to various CPU models without requiring manufacturer-specific bridge chips, thereby enabling manufacturers to choose from a broader range of components while maintaining reliable core unlocking functionality.

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Device complexity

If the south bridge chip directly regulates the clock signal duty cycle to unlock cores, then the unlocking process is simplified, but the system requires specific chip series increasing cost

Engineering Contradiction:
Improveunlocking process complexityVSAvoidchip series requirement
Core Design Contradiction:
Device complexityVSEase of manufacture

Solution Approach 1:

The clock signal regulation and core unlocking functions are extracted from the south bridge chip and transferred to the GPIO control device. The GPIO device generates the necessary control signals to regulate the clock signal duty cycle, maintaining the simplified unlocking process while eliminating the requirement for specific expensive bridge chip series.

Inventive Principle:
Principle #2Taking out (Extraction)

Data Source

PatentUS8972711B2CPU core unlocking device applied to computer system
Publication Date: 2015.03.03 ASUSTEK COMPUTER INC
  • US8972711B2 patent drawing
  • US8972711B2 patent drawing
  • US8972711B2 patent drawing

AI summary

A CPU core unlocking device applied to a computer system is provided. The core unlocking device includes a CPU having a plurality of signal terminals and a core unlocking executing unit having a plurality of GPIO ports connected with the corresponding signal terminals of the CPU. The GPIO ports of the core unlocking executing unit generate and transmit and transmit a combination of core unlocking signal to the signal terminals of the CPU to unlock the CPU core.