GPIO Output Circuit Isolation for Multi-Supply Backflow Prevention
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Solution Overview
Problem
Existing GPIO circuits face issues with chip malfunction and damage due to backflow caused by body diodes when multiple power supply voltages are present, leading to improper transistor operation.
Innovation Solution
The GPIO circuit incorporates a series connection of NMOS and PMOS transistors with a gate drive circuit to ensure simultaneous turning ON/OFF of transistors, using a dead-time control circuit to isolate the operating voltage output terminal from the GPIO pin, and includes a voltage selection circuit to manage multiple power supplies effectively.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a single PMOS transistor is used in the output circuit, then the device complexity is low, but backflow occurs causing chip malfunction and damage
Solution Approach 1:
The patent divides the single PMOS transistor into two series-connected PMOS transistors (first PMOS and second PMOS). This segmentation allows the body diodes of each transistor to be individually managed, preventing backflow by ensuring that when one PMOS is turned off, its body diode cannot conduct due to the series connection configuration. The segmentation resolves the contradiction by improving reliability through backflow prevention while accepting increased device complexity as a necessary trade-off.
Solution Approach 2:
The patent introduces a node (common connection point between first PMOS and second PMOS) that acts as an intermediary in the output circuit. This node serves as a buffer that isolates the body diode effects of the two PMOS transistors from each other, preventing the backflow path that would exist in a single-transistor configuration. The intermediary structure enables reliable operation by blocking harmful backflow currents while maintaining the push-pull output functionality.
2Adaptability or versatility
If multiple power supply voltages are supported, then the adaptability is improved, but backflow risk increases causing transistor malfunction
Solution Approach 1:
The series connection of two PMOS transistors segments the voltage path, allowing each transistor to handle a portion of the voltage difference between multiple power supplies. This segmentation prevents any single transistor from experiencing excessive voltage stress that could cause backflow through its body diode, thereby maintaining reliability while supporting multiple power supply voltages and improving adaptability.
Solution Approach 2:
The patent changes the electrical parameters (voltage distribution) across the transistors by using series connection. This allows the circuit to adapt to different power supply voltage combinations while maintaining safe operating conditions for each transistor, preventing backflow by ensuring voltage differences do not exceed body diode breakdown thresholds.
Data Source
AI summary
This disclosure relates to a GPIO circuit having an output circuit. The output circuit includes a first NMOS transistor connected between a GPIO pin and a reference ground, and a first PMOS transistor and a second PMOS transistor coupled in series between an operating voltage output terminal and the GPIO pin. The proposed GPIO circuit is capable of effectively isolating the operating voltage output terminal from the GPIO pin. By adding an LED drive circuit and/or a high-voltage pull-up circuit to the GPIO circuit, the GPIO circuit can flexibly operate in various modes according to application needs.