GPIO Driver Level Shifting for Low-Latency Chip I/O
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Solution Overview
Problem
Conventional GPIO drivers experience higher propagation delays during under-drive operations due to the level shifter, which can fail to meet timing requirements for chip-to-chip communications.
Innovation Solution
A GPIO driver design that includes a level shifter module capable of performing level-boosting when the supply voltage is lower and operating as a buffer when it is higher, using a power switch to select between two supply voltages (VCCINT and VCCIO) to minimize signal propagation delay.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If the level shifter performs level-boosting operation to increase voltage level, then the voltage level of the signal is increased, but the propagation delay increases
Solution Approach 1:
The level shifter module dynamically switches between level-boosting operation and buffer operation based on the voltage level comparison between first supply voltage and second supply voltage. When first supply voltage is lower, it performs level-boosting; when first supply voltage is higher, it operates as a buffer, thereby adapting its function to minimize propagation delay while meeting voltage level requirements.
Solution Approach 2:
The invention changes the operating mode of the level shifter module by changing the voltage level relationship between first supply voltage and second supply voltage. When the voltage levels are reversed compared to conventional designs, the level shifter operates as a buffer instead of performing level-boosting, thereby reducing propagation delay while still meeting the timing requirements for chip-to-chip communications.
2Loss of time
If the level shifter operates as a buffer to reduce propagation delay, then the timing requirements are met, but the voltage level cannot be increased
Solution Approach 1:
The system dynamically adjusts the operating mode of the level shifter based on the voltage level relationship. When first supply voltage is higher than second supply voltage, the level shifter operates as a buffer to minimize propagation delay. When first supply voltage is lower, it switches to level-boosting mode to increase voltage level, thereby adaptively resolving the contradiction between speed and voltage level requirements.
Solution Approach 2:
The invention inverts the conventional voltage level relationship between first supply voltage and second supply voltage. By making the first supply voltage (to control logic) lower than or equal to the second supply voltage (to post-driver), the level shifter operates as a buffer instead of performing level-boosting, thereby reducing propagation delay while still meeting communication timing requirements.
Data Source
AI summary
The present invention provides a GPIO driver including a control logic, a level shifter module and a post-driver. The control logic supplied by a first supply voltage is configured to receive an input signal to generate a first signal. The level shifter module is configured to receive the first signal to generate a second signal. The post-driver supplied by a second supply voltage is configured to receive the second signal to generate an output signal. When the first supply voltage is lower than the second supply voltage, the level shifter module performs a level-boosting operation to increase a voltage level of the first signal to generate the second signal; and when the first supply voltage is greater than the second supply voltage, the level shifter module operates as a buffer, and the voltage level of the second signal is the same as the voltage level of the first signal.