GPIO Mux Dynamic Port Configuration for Panel ASIC
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Solution Overview
Problem
Conventional ASICs face limitations in functionality due to physical I/O pin scarcity and packaging constraints, making it difficult to implement desired functionality and requiring expensive redesigns for different configurations.
Innovation Solution
Dynamically configurable routing logic between physical I/O ports and special purpose I/O within a panel ASIC, allowing for multiple routing configurations, including coupling special purpose outputs to physical I/O ports, input signals to special purpose inputs, and independent interrupt triggering, enabling flexible and on-the-fly reconfiguration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional ASIC designs use fixed dedicated I/O pin assignments, then each function has reliable I/O access, but the number of required physical I/O pins increases beyond packaging capabilities
Solution Approach 1:
The patent implements GPIO mux circuits that allow a single physical I/O pin to serve multiple special purpose functions through dynamic configuration. Instead of dedicating separate pins to each function (such as interrupt inputs, button inputs, or other control signals), the system uses a shared pool of general-purpose I/O pins that can be dynamically assigned to different functions based on operational mode, thereby reducing the total pin count while maintaining full functional capability
Solution Approach 2:
The patent employs dynamic configuration mechanisms where the assignment of physical I/O pins to special purpose functions can change at runtime. Configuration registers and control logic enable the system to reassign GPIO pins to different functions (e.g., switching between interrupt input mode, button input mode, or other control modes) based on the current operational requirements, providing adaptability without requiring dedicated pins for each possible function
2Adaptability or versatility
If a single ASIC design is made dynamically configurable, then adaptability to different applications improves, but device complexity increases
Solution Approach 1:
The patent divides the configuration system into modular components: individual GPIO mux circuits for each I/O pin, separate configuration registers for each GPIO bank, and function-specific control logic. This segmentation allows each component to be independently configured and managed, reducing the overall complexity burden by breaking down the configuration task into manageable units rather than requiring a monolithic complex control structure
Solution Approach 2:
The patent introduces configuration registers and control logic as intermediary elements between the physical I/O pins and the special purpose functions. These intermediaries manage the dynamic assignment process by holding configuration data and controlling the mux circuits, thereby simplifying the interface between the configurable GPIO subsystem and the rest of the ASIC while enabling adaptability
Data Source
AI summary
Dynamically configurable routing logic coupled between physical I/O ports and special purpose I/O associated with functions within a panel ASIC is disclosed that provide different routing configurations between the physical I/O ports and the special purpose I/O. In one routing configuration, any special purpose output can be coupled to one or more physical I/O ports, providing flexibility to route any functional I/O to any physical I/O port. In a second routing configuration, any input signal on a physical I/O port can be coupled to one or more special purpose inputs. In a third routing configuration, the input signals on a number of physical I/O ports can be configured to independently assert a single special purpose input for interrupt triggering. The dynamically configurable nature of the routing logic allows routing to be changed on the fly.