GPIO Pad Protection via Voltage Linger Detection
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Integrated circuits face issues such as contention and functional failures due to improper usage of GPIO pads, leading to potential damage from electromigration and noise-induced glitches, which existing technologies have not adequately addressed.
Innovation Solution
The implementation of a reliability detector system using comparators and a programmable counter to detect voltage linger times between CMOS thresholds, disabling input and output buffers to prevent damage and glitches, and enabling them only when the situation is resolved.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the GPIO pad is driven by both the output buffer and external circuitry at different values, then the GPIO pad can be used for bidirectional communication, but contention occurs causing permanent damage due to electromigration
Solution Approach 1:
The reliability detector continuously monitors the pad voltage before damage can occur. When contention is detected (voltage between thresholds for excessive time), the detector proactively disables the output buffer before electromigration damage can happen, preventing the harmful effect while allowing normal bidirectional operation to continue
Solution Approach 2:
The reliability detector creates a feedback loop that monitors pad voltage and provides real-time information about contention conditions. This feedback enables the system to detect and respond to improper usage patterns, disabling protection only when needed while maintaining normal operation during legitimate bidirectional communication
2Adaptability or versatility
If the input pad terminal is driven with signals having slow ramp rates, then the pad can interface with external devices having different switching characteristics, but noise causes glitches at the input buffer resulting in functional failures
Solution Approach 1:
The reliability detector monitors the pad voltage transition in advance and detects when a slow ramp rate causes the voltage to linger between thresholds. When excessive transition time is detected, the system proactively disables the input buffer before noise can cause glitches, preventing functional failures while allowing slow-ramping signals to continue
Solution Approach 2:
The detector provides feedback about the actual transition characteristics of incoming signals. This enables the system to distinguish between legitimate slow-ramping signals from external devices and problematic signals that would cause glitches, maintaining compatibility while protecting against failures
3Reliability
If a reliability detector with comparators and programmable counter is added to detect and protect against contention and slow ramping, then pad reliability is improved, but device complexity increases
Solution Approach 1:
The reliability detector is designed to handle multiple types of pad usage problems (contention on bidirectional pads, slow ramping on input pads) using the same basic circuit architecture of comparators, counter, and gating logic. This multi-functional design provides comprehensive protection without requiring separate dedicated circuits for each protection scenario
Solution Approach 2:
The programmable counter allows the detection thresholds and timing parameters to be configured based on specific application requirements. This parameter adjustability enables the same circuit to adapt to different pad types and external device characteristics, providing reliable protection across various scenarios without requiring hardware changes
Data Source
Figure 1
Figure 2
Figure 3
AI summary
An integrated circuit includes a signal pad, an output buffer having an output coupled to the signal pad and having an enable input, an input buffer having an input coupled to the signal pad and having an enable input, a counter, and a gating circuit. The counter is enabled to start counting down a predetermined count value when a voltage on the signal pad is both higher than a predetermined low threshold voltage and lower than a predetermined high threshold voltage, wherein the predetermined low threshold voltage corresponds to a threshold below which a voltage corresponds to a logic level zero and the predetermined high threshold voltage corresponds to a threshold above which a voltage corresponds to a logic level one. The gating circuit is configured to, in response to the counter expiring, disable the input buffer and the output buffer.