GPIO Timestamp Synchronization for Independent SoC Time Bases
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Solution Overview
Problem
Synchronizing independent systems-on-chip (SoCs) in electronic devices with independent time bases is challenging, requiring efficient and low-firmware-overhead methods.
Innovation Solution
Implementing a technique where a primary SoC asserts a GPIO connection to a secondary SoC, recording timestamps for synchronization, and calculating a clock offset using inter-SoC messaging to align time bases.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional synchronization methods are used between independent SoCs, then synchronization can be achieved, but firmware overhead becomes excessive
Solution Approach 1:
The patent extracts the timing reference function from the secondary SoC's independent clock and relocates it to the primary SoC's GPIO timestamp. By asserting a GPIO line at a known clock edge and recording the timestamp, the system eliminates the need for complex firmware-based time synchronization protocols, reducing firmware overhead while maintaining synchronization accuracy
Solution Approach 2:
The patent introduces a GPIO connection as an intermediary between the primary and secondary SoCs. This physical signal serves as a common reference point that both SoCs can observe, allowing them to synchronize their time bases without requiring extensive firmware communication or complex synchronization protocols
2Adaptability or versatility
If independent time bases are used in each SoC, then each SoC operates autonomously, but timing alignment between SoCs becomes difficult
Solution Approach 1:
The patent performs preliminary action by having the primary SoC assert the GPIO signal at a precisely known clock edge before the secondary SoC needs to synchronize. This advance timing reference allows the secondary SoC to calculate the offset without disrupting its autonomous operation, maintaining both autonomy and precision
Solution Approach 2:
The patent implements feedback by having the secondary SoC measure the timestamp difference between receiving the GPIO assertion and its own clock, then use this measured offset to adjust its time base. This feedback mechanism enables continuous timing alignment while preserving SoC autonomy
Data Source
AI summary
An electronic eyewear device includes first and second systems-on-chip (SoCs) having independent time bases. The first and second SoCs are connected by a shared general purpose input/output (GPIO) connection and an inter-SOC interface. The first and second SoCs are synchronized to each other by the first SoC asserting the shared GPIO connection to the second SoC where assertion of the message to the shared GPIO connection triggers an interrupt request (IRQ) at the second SoC. The first SoC records a first timestamp for assertion of the message to the GPIO connection, and the second SoC records a second timestamp of receipt of the IRQ. The first SoC sends a message including the first timestamp to the second SoC over the inter-SoC interface. The second SoC calculates a clock offset between the first and second SoCs as a difference between the first and second timestamps.