Multi-SoC Electronic Eyewear Synchronization Using GPIO Timestamps
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Solution Overview
Problem
Existing electronic devices with multiple systems-on-chip (SoCs) face challenges in synchronizing their independent time bases, which can lead to processing inefficiencies and inconsistencies in operations.
Innovation Solution
Synchronizing SoCs by sharing timestamps recorded upon assertion of a general purpose input/output (GPIO) connection, where one SoC asserts the GPIO to trigger an interrupt request at another SoC, and calculates the clock offset using recorded timestamps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional synchronization methods are used between multiple SoCs, then synchronization accuracy can be maintained, but firmware overhead and system complexity increase
Solution Approach 1:
The patent extracts the timestamp recording function from the complex firmware synchronization protocol and implements it directly in hardware within the GPIO controller. The hardware automatically captures timestamps when GPIO assertions occur, eliminating the need for sophisticated firmware synchronization mechanisms while maintaining high synchronization accuracy between multiple SoCs.
Solution Approach 2:
The patent introduces a hardware-based GPIO assertion mechanism as an intermediary event source. Instead of having SoCs directly exchange synchronization signals through complex firmware protocols, the GPIO assertion serves as a hardware-mediated event that automatically generates timestamps, simplifying the synchronization process while preserving accuracy.
2Productivity
If hardware-based timestamp recording is implemented, then processing efficiency improves, but implementation complexity increases
Solution Approach 1:
The patent integrates the timestamp recording function into the existing GPIO controller hardware, making the GPIO controller multi-functional. The same GPIO controller that handles general-purpose input/output operations also automatically records timestamps for synchronization events, eliminating the need for separate dedicated timestamp hardware and reducing overall implementation complexity.
Solution Approach 2:
The patent merges the timestamp recording functionality with the GPIO controller hardware. By combining these functions into a single hardware component, the patent achieves efficient timestamp capture without the overhead of separate dedicated timestamp hardware, thereby improving processing efficiency while keeping implementation complexity manageable.
Data Source
AI summary
An electronic eyewear device includes first and second systems-on-chip (SoCs) having independent time bases. The first and second SoCs are connected by a shared general purpose input/output (GPIO) connection and an inter-SoC interface. The first and second SoCs are synchronized to each other by the first SoC asserting the shared GPIO connection to the second SoC where assertion of the message to the shared GPIO connection triggers an interrupt request (IRQ) at the second SoC. The first SoC records a first timestamp for assertion of the message to the GPIO connection, and the second SoC records a second timestamp of receipt of the IRQ. The first SoC sends a message including the first timestamp to the second SoC over the inter-SoC interface. The second SoC calculates a clock offset between the first and second SoCs as a difference between the first and second timestamps.