GPIO Voltage-Domain Control Using ID-Based Cross-Domain Writes

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Solution Overview

Problem

Integrated circuits face challenges in efficiently transferring data between different voltage domains due to the large size and high power consumption of traditional voltage level shifters, which can degrade reliability and increase power dissipation.

Innovation Solution

The implementation of a method that uses a reduced number of voltage level shifters to program General Purpose Input/Output (GPIO) interfaces by encoding identifiers and sending bit values across voltage domains, allowing for simultaneous configuration of multiple GPIOs with a single write pulse, thereby reducing the number of voltage shifters needed and minimizing power consumption.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If traditional voltage level shifters are used to transfer data between voltage domains, then data transfer reliability is maintained, but power consumption increases and IC size increases

Engineering Contradiction:
Improvedata transfer reliabilityVSAvoidpower consumption
Core Design Contradiction:
ReliabilityVSUse of energy by moving object

Solution Approach 1:

The patent extracts only the essential control information (bit values and identifiers) from the data transfer process, separating it from the need for full-duplex voltage-level-shifted communication. By taking out only the necessary control bits and transmitting them through a simplified mechanism, the system maintains reliability while eliminating the power consumption overhead of traditional level shifters.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent uses copying by transmitting identifier information that represents the control bit positions, rather than directly transferring all control signals through voltage level shifters. The identifier acts as a reference or copy that allows the receiving domain to reconstruct the necessary control information without requiring direct voltage-level-shifted paths for every control signal.

Inventive Principle:
Principle #26Copying

2Productivity

If traditional voltage level shifters are used to transfer data between voltage domains, then data transfer is achieved, but IC size increases

Engineering Contradiction:
Improvedata transfer capabilityVSAvoidIC size
Core Design Contradiction:
ProductivityVSArea of stationary object

Solution Approach 1:

The patent extracts only the essential control information (bit values and identifiers) from the data transfer process, separating it from the need for full-duplex voltage-level-shifted communication. By taking out only the necessary control bits and transmitting them through a simplified mechanism, the system maintains reliability while eliminating the power consumption overhead of traditional level shifters.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent introduces a new dimension to data transfer by adding identifier fields that encode control bit positions. This dimensional addition allows the system to convey more information through the same physical channels, reducing the need for additional hardware components and thereby reducing IC size.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

3Adaptability or versatility

If multiple voltage level shifters are used to program multiple GPIOs, then configuration capability is provided, but power consumption increases

Engineering Contradiction:
ImproveGPIO configuration capabilityVSAvoidpower consumption
Core Design Contradiction:
Adaptability or versatilityVSUse of energy by moving object

Solution Approach 1:

The patent merges the configuration of multiple GPIOs into a single unified operation. By combining multiple control bit transfers into one simultaneous write pulse that affects multiple I/O interfaces at once, the system achieves full GPIO configuration capability while using a single voltage domain transition event, thereby reducing power consumption compared to individual GPIO configurations.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The patent creates a universal configuration mechanism that can program any combination of GPIOs across multiple I/O interfaces through a single operation. The identifier-based addressing system provides multi-functionality, allowing the same hardware mechanism to configure different GPIOs dynamically without requiring dedicated control paths for each GPIO, thus reducing overall power consumption.

Inventive Principle:
Principle #6Universality (Multi-functionality)

4Productivity

If a single write pulse configures multiple GPIOs simultaneously, then programming efficiency increases, but control complexity increases

Engineering Contradiction:
Improveprogramming efficiencyVSAvoidcontrol complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent introduces an intermediary identifier field that mediates between the single write pulse and the multiple GPIO targets. This identifier acts as an intermediate representation that encodes which specific control bits should be updated, allowing the system to achieve efficient simultaneous configuration while managing complexity through structured data encoding rather than complex control logic.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS11791824B1Voltage domain GPIO control
Publication Date: 2023.10.17 APPLE INC
  • US11791824B1 patent drawing
  • US11791824B1 patent drawing
  • US11791824B1 patent drawing

AI summary

An integrated circuit (IC) includes an Input/Output (I/O) interface, first-domain circuitry and second-domain circuitry. The I/O interface is coupled to a first voltage domain and is configurable by a set of control bits. The second-domain circuitry is coupled to a second voltage domain and is configured to generate a bit value for a control bit among the control bits, to generate a multi-bit identifier (ID) of the control bit, and to transmit the bit value and the multi-bit ID. The first-domain circuitry is coupled to the first voltage domain and is configured to receive the bit value and the multi-bit ID, to identify the control bit from the multi-bit ID, and to configure the control bit of the I/O interface with the bit value.