GPON Data Double Oversampling Phase Locking

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Solution Overview

Problem

The existing GPON (Gigabit Passive Optical Network) technology faces challenges in maintaining phase locking during data transmission at higher uplink rates, specifically 2.48832 Gbps, due to the inability of SerDes clock frequency in receiving terminals to meet the required sampling frequency.

Innovation Solution

A data double oversampling method that shifts the initial sampling phase of GPON frames to determine the optimal sampling phase, ensuring it is closer to the middle phase of the preamble, allowing for stable phase locking within the specified time without requiring hardware changes.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If the uplink rate is upgraded to 2.48832 Gbps, then the data transmission speed is improved, but the SerDes clock frequency cannot meet the sampling frequency requirements

Engineering Contradiction:
Improveuplink data transmission rateVSAvoidphase locking stability
Core Design Contradiction:
SpeedVSReliability

Solution Approach 1:

The patent implements dynamic sampling phase adjustment by introducing a sampling phase correction module that continuously optimizes the sampling phase based on detected signal characteristics. This dynamic adaptation allows the system to maintain reliable phase locking at the higher 2.48832 Gbps uplink rate without requiring hardware changes to the SerDes clock frequency.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent changes the sampling frequency parameter from 4x oversampling to 2x oversampling to match the upgraded data rate. By adjusting this key parameter and compensating through software-based phase correction algorithms, the system achieves reliable operation at the new transmission speed without hardware modifications.

Inventive Principle:
Principle #35Parameter changes

2Measurement precision

If 4 times oversampling is used, then the phase locking accuracy is improved, but the hardware cannot support the required clock frequency for 2.48832 Gbps transmission

Engineering Contradiction:
Improvesampling accuracyVSAvoidhardware configuration
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent replaces the hardware-based 4x oversampling mechanism with a software-based phase correction system. Instead of increasing clock frequency hardware capabilities, the invention uses algorithmic phase adjustment to achieve equivalent or superior sampling accuracy, thereby avoiding hardware complexity increases.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

Solution Approach 2:

The patent creates a virtual 4x oversampling effect through software by performing multiple sampling operations at 2x rate and selecting the optimal sample based on phase correction calculations. This virtual copying approach achieves the desired precision without the hardware overhead of actual 4x oversampling.

Inventive Principle:
Principle #26Copying

3Device complexity

If the sampling phase is not optimized, then the system complexity is reduced, but the phase locking time exceeds the protocol specification

Engineering Contradiction:
Improvesampling phase adjustment mechanismVSAvoidphase locking time
Core Design Contradiction:
Device complexityVSLoss of time

Solution Approach 1:

The patent implements preliminary sampling phase correction during the preamble detection phase. By pre-adjusting the sampling phase before actual data reception begins, the system achieves rapid phase locking within protocol specifications without adding complexity to the ongoing data processing path.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent introduces an intermediary sampling phase correction module that acts as a bridge between the received signal and the data processing pipeline. This intermediary component performs the time-consuming phase adjustment operations separately, allowing the main data path to remain simple and efficient while still achieving fast overall phase locking.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS20240334099A1Data double oversampling method, system device and storage medium
Publication Date: 2024.10.03 SHENZHEN PANGO MICROSYST CO LTD
  • US20240334099A1 patent drawing
  • US20240334099A1 patent drawing
  • US20240334099A1 patent drawing

AI summary

A data double oversampling method includes: obtaining the initial sampling phase of two adjacent bits of the preamble in a GPON frame and the phase label of each initial sampling phase. Based on whether the adjacent phase labels of the target jump edge before and after shifting are equal and whether the first reference sampling phase is located at the target jump edge, shifting each sampling phase after shift again to obtain the optimal sampling phase corresponding to the two adjacent bits, in order to sample the valid data. The method samples the valid data by determining the optimal sampling phase at the preamble, and can stably complete the phase locking of the recovered data within the time specified in the protocol; and there is no need to change hardware devices which saves costs.