GPP-Based PRN Code Generation for GNSS

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Solution Overview

Problem

Current Global Navigation Satellite System (GNSS) technologies rely on hardware-based PRN code generation, which is inflexible, costly, and power-intensive, and lacks the ability to efficiently accommodate evolving waveform requirements.

Innovation Solution

The implementation of a general-purpose processor (GPP) system that dynamically generates linear feedback shift register (LFSR) based PRN spreading code sequences, allowing for selection between short and long cycles and emulation of multiple LFSR for efficient PRN code chip generation, thereby reducing hardware requirements and power consumption.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If hardware-based PRN code generation is used, then reliability is improved, but device complexity and cost increase

Engineering Contradiction:
ImprovePRN code generation reliabilityVSAvoidhardware complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent replaces hardware-based PRN code generation circuits with a software-based implementation using a general-purpose processor. The LFSR algorithm is executed through software instructions, substituting the mechanical/hardware system with an information-processing system that achieves the same functional reliability through computational emulation rather than dedicated hardware circuits.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

Solution Approach 2:

The patent implements PRN code generation by copying the behavior of hardware LFSR circuits through software emulation. The GPP executes instructions that replicate the exact functional behavior of hardware LFSR, producing identical PRN code sequences without requiring physical hardware components, thus reducing device complexity while maintaining reliability.

Inventive Principle:
Principle #26Copying

2Reliability

If hardware-based PRN code generation is used, then reliability is improved, but power consumption increases

Engineering Contradiction:
ImprovePRN code generation reliabilityVSAvoidpower consumption
Core Design Contradiction:
ReliabilityVSUse of energy by moving object

Solution Approach 1:

The patent substitutes power-intensive hardware circuits with low-power software execution on a general-purpose processor. The GPP consumes significantly less power than dedicated hardware PRN generators, and this power consumption can be dynamically adjusted based on operational requirements, while still achieving reliable PRN code generation through accurate software emulation of the LFSR algorithm.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

3Speed

If hardware-based PRN code generation is used, then processing speed is improved, but adaptability to waveform updates deteriorates

Engineering Contradiction:
ImprovePRN code generation speedVSAvoidadaptability to waveform updates
Core Design Contradiction:
SpeedVSAdaptability or versatility

Solution Approach 1:

The patent implements dynamic adaptability by allowing the PRN code generation parameters (such as LFSR initial states, feedback polynomials, and code lengths) to be dynamically reconfigured through software updates. The GPP can change its operational parameters without hardware modifications, enabling adaptation to evolving waveform requirements while maintaining high processing speeds through optimized software algorithms and efficient processor execution.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The general-purpose processor provides universal functionality that can accommodate multiple PRN code generation configurations and waveform types through a single software platform. The same GPP can generate different PRN sequences by loading different software configurations, making the system highly adaptable to future waveform updates without requiring dedicated hardware for each specific application.

Inventive Principle:
Principle #6Universality (Multi-functionality)

4Speed

If hardware-based PRN code generation is used, then processing speed is improved, but cost increases

Engineering Contradiction:
ImprovePRN code generation speedVSAvoidmanufacturing cost
Core Design Contradiction:
SpeedVSEase of manufacture

Solution Approach 1:

The patent reduces manufacturing cost by replacing expensive dedicated hardware PRN generation circuits with inexpensive software execution on a standard general-purpose processor. The hardware cost is eliminated in favor of software licensing and processor costs, which are significantly lower, while maintaining high processing speeds through efficient algorithm implementation and processor optimization.

Inventive Principle:
Principle #26Copying

Solution Approach 2:

The substitution of hardware circuits with software implementation eliminates the need for expensive hardware manufacturing, assembly, and quality control processes. The GPP-based solution uses off-the-shelf processor hardware that is cheaper to produce at scale, while the PRN generation functionality is achieved through software that can be efficiently developed, tested, and deployed without the complexity of hardware engineering.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

Data Source

PatentUS9897702B2Generation of linear feedback shift register based pseudo random noise (PRN) spreading code sequence for global navigation satellite system
Publication Date: 2018.02.20 THE BOEING CO
  • US9897702B2 patent drawing
  • US9897702B2 patent drawing
  • US9897702B2 patent drawing

AI summary

Technology to generation of linear feedback shift register based PRN spreading code sequence using a processor device in a computing system is disclosed. A system is provided for generating a GNSS code sequence in a computer system, the system comprising one or more logic circuits configured to at least: receive a plurality of waveform generation parameters; select between a short pseudo-random noise (PRN) cycle and a long PRN cycle according to at least one of the plurality of waveform generation parameters; and emulate a plurality of linear feedback shift registers (LFSR) for generating a block of PRN code chips.