GPS Decimation Circuitry Integrating Signal Samples
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Solution Overview
Problem
Low sampling rates in GPS receivers result in obscured code transitions due to limited pre-sampling bandwidth, leading to reduced performance, as they struggle to maintain high Signal-to-Noise Ratio (SNR) and are limited by the need for low-pass filtering to prevent aliasing.
Innovation Solution
A decimation system that integrates digital baseband signals over code chips with varying start times but common duration, generating chip-phase matched filters, allowing for reduced sampling rates without pre-sampling filtering, thereby improving performance by maintaining high SNR and reducing processor throughput.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If low sampling rate is used to reduce processor throughput requirements, then processor load is reduced, but pre-sampling bandwidth is limited causing code transitions to be obscured and performance to deteriorate
Solution Approach 1:
The patent applies preliminary action by performing integrations of the digital baseband signal over multiple code chip durations before decimation. These integrations accumulate signal energy and enhance code transition characteristics prior to sampling rate reduction, ensuring that code transitions remain detectable even at lower sampling rates. The integration process prepares the signal in advance so that subsequent decimation does not obscure critical transition information.
2Reliability
If low-pass filtering is applied prior to decimation to prevent aliasing, then aliasing is prevented, but pre-sampling bandwidth is reduced obscuring code transitions
Solution Approach 1:
The patent extracts the aliasing prevention function from the traditional low-pass filter and relocates it to the integration process. By integrating the signal over code chip durations, the system inherently suppresses high-frequency components that would cause aliasing, while preserving the bandwidth necessary to capture code transitions. This extraction eliminates the need for separate low-pass filtering that would otherwise obscure transitions.
Solution Approach 2:
The integration process serves as an intermediary between the raw digital baseband signal and the decimated output. This intermediary operation performs dual functions: it accumulates signal energy to maintain transition detectability while simultaneously filtering out high-frequency aliasing components. The integration acts as a mediator that reconciles the conflicting requirements of aliasing prevention and transition preservation without requiring aggressive low-pass filtering.
3Measurement precision
If higher sampling rate is used to maintain pre-sampling bandwidth and code transition visibility, then code transition detection is improved, but processor throughput requirements increase
Solution Approach 1:
The patent performs signal preparation in advance through integrations that accumulate energy over code chip durations. This preliminary action enhances the visibility of code transitions before decimation occurs, allowing the system to use lower sampling rates without sacrificing transition detection accuracy. The advance preparation eliminates the need for high sampling rates to maintain transition visibility.
Solution Approach 2:
The patent changes the temporal parameter of signal processing by integrating over extended code chip durations rather than sampling at high rates. This parameter change transforms the approach from time-domain high-rate sampling to energy accumulation over longer intervals, thereby maintaining transition detection capability while reducing the required sampling rate and processor throughput.
Data Source
AI summary
A system and method for sampling signal in a Global Positioning System (GPS) receiver or Code Division Multiple Access (CDMA) communication device are provided. In general, decimation circuitry is provided. The decimation circuitry includes filtering circuitry that performs a number of integrations of an input signal for each code chip, where each the number of integrations has a different start time but has a common integration period equal to the duration of a code chip. Each of the integrations provides an output sample of the input signal for one of a corresponding number of chip-phases. The output samples for the chip-phases are provided to processing circuitry for numerous code chips. The processing circuitry processes the output samples corresponding to a select one of the chip-phases such that the sampling rate of the digital signal is reduced.