GPS Processing Arrangement With Independent Counter

Solution Overview

Problem

In software GPS systems, microprocessor clock speed changes can cause DMA transfer interruptions, leading to FIFO overflow and loss of GPS signal samples, rendering the cumulative count of samples invalid and necessitating a restart of the GPS decoding process, which takes several seconds to acquire a new position fix.

Innovation Solution

A 4-bit counter connected to the GPS RF front end increments on each clock cycle and a 32-bit counter peripheral integrated with the microprocessor, allowing for independent counting of GPS signal samples, enabling recovery of the cumulative count and prompt determination of a position fix without restarting the decoding process.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Use of energy by moving object

If the microprocessor clock speed is changed to match current processing requirements, then power consumption is reduced, but DMA transfer is interrupted causing FIFO overflow and data loss

Engineering Contradiction:

Improvepower consumptionVSAvoiddata transfer reliability

Core Design Contradiction:

Use of energy by moving objectVSReliability

Solution Approach 1:

The system pre-allocates a larger circular buffer (e.g., 64KB or 128KB) to accommodate potential data accumulation during clock speed transitions. This preliminary preparation ensures that even when DMA transfer is interrupted for over 100 microseconds during PLL stabilization, the FIFO will not overflow and no GPS signal samples will be lost, maintaining data transfer reliability while allowing dynamic clock speed changes for power savings

Inventive Principle:

Principle #10Preliminary action

2Use of energy by moving object

If the microprocessor clock speed is changed, then power consumption is reduced, but the cumulative count of samples becomes invalid requiring restart of decoding process

Engineering Contradiction:

Improvepower consumptionVSAvoidtime to acquire position fix

Core Design Contradiction:

Use of energy by moving objectVSLoss of time

Solution Approach 1:

An independent counter circuit is introduced as an intermediary component that operates separately from the microprocessor and DMA controller. This counter continues to increment during clock speed transitions and DMA interruptions, maintaining an accurate cumulative count of GPS signal samples. The independence of this counter from the microprocessor clock ensures it remains valid even when the processor changes speed for power management, eliminating the need to restart the decoding process and reducing time loss

Inventive Principle:

Principle #24Intermediary (Mediator)

3Adaptability or versatility

If DMA transfer is halted for PLL stabilization, then clock speed change is achieved, but FIFO overflow occurs and data is lost

Engineering Contradiction:

Improveclock speed adaptabilityVSAvoidGPS signal sample loss

Core Design Contradiction:

Adaptability or versatilityVSLoss of information

Solution Approach 1:

The system pre-allocates a larger circular buffer (e.g., 64KB or 128KB) to accommodate potential data accumulation during clock speed transitions. This preliminary preparation ensures that even when DMA transfer is interrupted for over 100 microseconds during PLL stabilization, the FIFO will not overflow and no GPS signal samples will be lost, maintaining data transfer reliability while allowing dynamic clock speed changes for power savings

Inventive Principle:

Principle #10Preliminary action

Data Source

PatentUS7619560B2GPS processing arrangement

Publication Date: 2009.11.17 NXP BV

AI summary

A software GPS processing arrangement comprising a FIFO buffer for receiving a stream of the GPS signal samples, a memory, a DMA controller for transferring the GPS signal samples from the FIFO buffer to the memory, a CPU running GPS signal processing software configured to retrieve the GPS signal samples from the memory and process them to obtain a position fix, and a counter operating independently of the DMA controller and the CPU for keeping count of the number of streamed GPS signal samples.