GPSTP Thread Memory for Multi-Thread State Management
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Solution Overview
Problem
The existing general purpose set theoretic processor (GPSTP) faces limitations in versatility due to the need to receive and assemble interleaved data streams from multiple sources, requiring significant memory and resources, which hinders its ability to maintain speed and capacity.
Innovation Solution
The introduction of a thread memory system that allows for state save-and-restore functionality, reducing memory bits and logic gates by one-third and one-half respectively, and modifying cell structures to implement multi-thread capabilities without compromising throughput.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the GPSTP implements multi-thread functionality to process interleaved data streams from multiple sources, then the processor's versatility and data processing capability are improved, but the memory requirements and resource consumption increase significantly
Solution Approach 1:
The patent segments the state storage requirement by processing threads independently. Each thread maintains its own state in separate memory locations, allowing the system to handle multiple interleaved data streams without requiring a monolithic large memory structure. This segmentation enables the GPSTP to process multiple threads concurrently while reducing total memory footprint through selective state preservation.
Solution Approach 2:
The patent implements preliminary state saving before context switches. When a thread is interrupted or switched, its state is saved in advance to memory, and when the thread resumes, the state is restored from the saved location. This preliminary action mechanism allows the GPSTP to maintain thread context without requiring continuous memory allocation for all possible thread states simultaneously.
2Adaptability or versatility
If the GPSTP preserves state externally to maintain thread context during interleaved processing, then thread functionality is improved, but the processing speed decreases due to state save-and-restore operations
Solution Approach 1:
The patent introduces an intermediary memory structure that facilitates efficient state transfer between threads. This intermediary state memory allows rapid save-and-restore operations during context switches, minimizing the impact on processing speed. The intermediary structure enables thread context preservation without requiring complex external state management that would slow down the processing pipeline.
3Reliability
If the GPSTP uses traditional memory structures to store thread states, then state preservation is achieved, but the number of memory bits and logic gates increases by two-thirds and one-half respectively
Solution Approach 1:
The patent applies partial state preservation by saving only the necessary thread state information required for context restoration, rather than saving the complete thread state. This selective state saving reduces the number of memory bits and logic gates needed while maintaining sufficient reliability for thread context preservation. The system saves only the essential control and state information needed to resume thread execution.
Solution Approach 2:
The patent changes the parameter representation of thread state from traditional comprehensive storage to a condensed format that preserves essential state information with reduced resource consumption. By modifying how state parameters are stored and represented, the system achieves state preservation with significantly fewer memory bits and logic gates, reducing overall device complexity while maintaining functional reliability.
Data Source
AI summary
Multiple thread functionality in a general purpose set theoretic processor (GPSTP) is implemented by addition of a thread memory for processing multiple interleaved data input streams to enable state save-and-restore functionality. The thread memory is functionally distributed among three parts of the GPSTP that change state during execution. The system structure minimizes the number of bits required to be saved and restored, and cell structures are configured implement the multi-thread functionality.