GPU 64-Bit 2D Block Loads With Transpose for Matrix Multiplication
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Solution Overview
Problem
Current parallel rendering graphics architectures lack hardware support for 64-bit data size transpose operations in two-dimensional block messages.
Innovation Solution
Implementing dedicated circuitry in graphics processing units (GPUs) to support 64-bit data size transpose operations for two-dimensional block loads, enabling efficient matrix multiplication in graphics processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If hardware support for 64-bit transpose operations is implemented, then processing efficiency for matrix multiplication is improved, but device complexity increases
Solution Approach 1:
The 64-bit transpose operation is divided into multiple 32-bit sub-operations. The block load message is split into two 32-bit portions, each processed through separate transpose logic units. This segmentation allows the use of existing 32-bit hardware infrastructure while achieving 64-bit functionality, thereby improving processing efficiency without proportionally increasing device complexity.
Solution Approach 2:
The patent extends existing 32-bit transpose operation capabilities into the 64-bit dimension by processing data in chunks. Rather than designing entirely new 64-bit transpose hardware, the solution processes 64-bit data by dividing it into 32-bit segments that can be handled by existing circuitry, effectively adding 64-bit capability through dimensional extension of the processing approach.
2Adaptability or versatility
If 64-bit block load with transpose is supported, then matrix multiplication capability is enhanced, but ease of operation remains unchanged
Solution Approach 1:
The hardware automatically performs the transpose operation as part of the block load process for 64-bit data. When a 64-bit block load message with transpose indication is received, the dedicated circuitry autonomously executes the transpose without requiring additional software intervention or complex programming, thereby enhancing matrix multiplication capability while maintaining ease of operation.
3Speed
If dedicated circuitry for 64-bit transpose is added, then processing speed is improved, but manufacturing complexity increases
Solution Approach 1:
The dedicated circuitry processes 64-bit transpose operations by segmenting them into 32-bit sub-operations that can be manufactured using existing process technologies. This segmentation approach allows the use of proven manufacturing processes and design libraries, thereby improving transpose operation speed while minimizing the increase in manufacturing complexity.
Data Source
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AI summary
An apparatus to facilitate 64-bit two-dimensional (2D) block load with transpose is disclosed. The apparatus includes a processor comprising processing resources; and load store pipeline hardware circuitry coupled to the processing resources, the load store pipeline hardware circuitry to receive a 64-bit two-dimensional (2D) block load message with transpose from the processing resources. The load store pipeline hardware circuitry comprising a load store pipeline sequencer to map rows of a block of memory corresponding to the 64-bit 2D block load message with transpose to 64-bit standard load messages; and load store pipeline return circuitry to: sequentially number general register files (GRFs) used for returning elements of the block of memory accessed by the 64-bit standard load messages to the processing resources; and return, to the processing resources, the sequentially numbered GRFs in response to the 64-bit 2D block load message with transpose.