8-bit Floating Point Graphics Processor with Stochastic Rounding
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Solution Overview
Problem
Current graphics processing units lack hardware support for performing operations using 8-bit floating point format operands, which are essential for efficient low-precision arithmetic in applications like artificial intelligence and machine learning.
Innovation Solution
Implementing a graphics processing unit architecture that supports 8-bit floating point format operations through dedicated circuitry for parallel computing, including stochastic rounding and systolic array operations, to enhance performance in low-precision data formats.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional graphics processors use fixed function computational units, then hardware complexity is reduced, but computational versatility and support for new data formats are limited
Solution Approach 1:
The patent implements a universal floating point processor that can handle multiple data formats (8-bit, 16-bit, 32-bit floating point) and various operations (add, subtract, multiply, divide, power, exponential) through a single integrated unit. This multi-functional design allows the same hardware to support both conventional graphics operations and AI/ML workloads requiring 8-bit floating point arithmetic, eliminating the need for separate dedicated hardware for each function.
Solution Approach 2:
The patent employs parameter changes by implementing dynamic precision control and flexible data type handling. The processor can switch between different floating point precisions (8-bit, 16-bit, 32-bit) based on the specific computational requirements, allowing efficient resource utilization while maintaining versatility across different application domains without requiring separate hardware for each precision level.
2Productivity
If graphics processors implement pipelining for parallel processing, then processing speed increases, but support for low-precision arithmetic operations is insufficient
Solution Approach 1:
The patent segments the floating point processor into specialized functional units including an 8-bit floating point add/subtract unit, multiply unit, divide unit, power unit, and exponential unit. Each segment is optimized for specific operations while working together within a pipelined architecture, enabling high-throughput parallel processing of low-precision arithmetic operations for AI/ML workloads.
Solution Approach 2:
The patent implements dynamic operation selection where the processor can adaptively choose between different computational paths based on the operation type and data precision requirements. The architecture dynamically switches between conventional high-precision processing and optimized 8-bit floating point operations, maintaining high parallel processing throughput while providing versatile low-precision arithmetic support when needed.
3Productivity
If conventional systems provide no hardware support for 8-bit floating point operations, then hardware simplicity is maintained, but computational efficiency for AI/ML applications is reduced
Solution Approach 1:
The patent implements self-service by providing dedicated hardware support specifically for 8-bit floating point operations that are commonly used in AI/ML applications. The hardware includes specialized units for addition, subtraction, multiplication, division, power, and exponential operations that automatically handle low-precision computations without requiring software emulation or complex workarounds, thereby improving computational efficiency while adding targeted hardware support only where needed.
Data Source
AI summary
An apparatus to facilitate supporting 8-bit floating point format for parallel computing and stochastic rounding operations in a graphics architecture is disclosed. The apparatus includes a processor comprising: a decoder to decode an instruction fetched for execution into a decoded instruction, wherein the decoded instruction is a matrix instruction that is to operate on 8-bit floating point operands to perform a parallel dot product operation; a scheduler to schedule the decoded instruction and provide input data for the 8-bit floating point operands in accordance with an 8-bit floating data format indicated by the decoded instruction; and circuitry to execute the decoded instruction to perform 32-way dot-product using 8-bit wide dot-product layers, each 8-bit wide dot-product layer comprises one or more sets of interconnected multipliers, shifters, and adders, wherein each set of multipliers, shifters, and adders is to generate a dot product of the 8-bit floating point operands.