GPU Barrier-Reduce Operation for Low-I/O Thread Synchronization
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Solution Overview
Problem
The traditional approach for scheduling map and reduce tasks in graphics processors involves barrier synchronization, which introduces significant I/O operations, reducing the performance of reduce operations due to write and read operations in the reduce phase.
Innovation Solution
A system and method that eliminates the read and write operations in the reduce phase by merging them into the barrier function, thereby optimizing reduce operations in graphics processors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If barrier synchronization is used for scheduling map and reduce tasks, then task coordination is achieved, but I/O overhead increases due to write and read operations
Solution Approach 1:
The patent merges the barrier synchronization function with the reduce operation itself. Instead of using separate barrier instructions followed by read/write operations, the reduce operation is integrated directly into the barrier function, allowing threads to perform reduction operations while waiting at the barrier point. This eliminates the need for separate I/O operations for both the barrier synchronization and the reduce phase, thereby reducing I/O overhead while maintaining task coordination.
2Reliability
If traditional barrier synchronization with separate read/write operations is used, then synchronization is achieved, but processing speed decreases due to I/O operations
Solution Approach 1:
The patent combines the barrier synchronization operation with the reduce operation into a single integrated function. Threads perform their reduction computations while waiting at the barrier, eliminating the need for separate read/write I/O operations that would otherwise be required. This integration allows synchronization to occur without the performance penalty of sequential I/O operations, thereby maintaining reliable synchronization while improving processing speed.
3Measurement precision
If separate read and write operations are performed in the reduce phase, then data accuracy is maintained, but operation complexity increases
Solution Approach 1:
The patent merges the read and write operations into the integrated barrier-reduce function. Instead of requiring separate instructions for reading data, performing reduction, and writing results, the operation is consolidated into a single barrier-reduce instruction that accomplishes all three tasks atomically. This reduces operation complexity while maintaining data accuracy through the atomic nature of the integrated operation.
Data Source
AI summary
Embodiments described herein provide a system, method, and apparatus to accelerate reduce operations in a graphics processor. One embodiment provides an apparatus including one or more processors, the one or more processors including a first logic unit to perform a merged write, barrier, and read operation in response to a barrier synchronization request from a set of threads in a work group, synchronize the set of threads, and broadcast a result of an operation specified in association with the barrier synchronization request.