GPU Burst Processing With Dedicated Sub-Processor
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The increasing power consumption and chip area requirements of GPU register files due to the use of SRAMs, which are not scaling efficiently with process developments, and the need to manage large numbers of parallel threads in GPUs.
Innovation Solution
Implementing a separate sub-processor within the GPU to execute atomically executable groups of instructions, using flip-flop based registers and a dedicated instruction cache to reduce SRAM access and optimize power and area efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If SRAM-based register files are used to support large numbers of parallel threads, then thread switching capability is improved, but power consumption and chip area increase
Solution Approach 1:
The processor is divided into two independent parts: a main processor that executes the main program and a sub-processor that executes bursts. Each processor has its own separate register file, allowing the sub-processor to use a smaller, more power-efficient register file while the main processor maintains full thread switching capability.
Solution Approach 2:
Burst instructions are extracted from the main program and executed separately by the sub-processor. This extraction allows frequently used instruction sequences to be executed independently without requiring thread context switching, thereby reducing power consumption while maintaining functionality.
2Adaptability or versatility
If SRAM-based register files are used to support large numbers of parallel threads, then thread switching capability is improved, but chip area increases
Solution Approach 1:
The processor is divided into two independent parts: a main processor that executes the main program and a sub-processor that executes bursts. Each processor has its own separate register file, allowing the sub-processor to use a smaller, more power-efficient register file while the main processor maintains full thread switching capability.
Solution Approach 2:
Burst instructions are extracted from the main program and executed separately by the sub-processor. This extraction allows frequently used instruction sequences to be executed independently without requiring thread context switching, thereby reducing power consumption while maintaining functionality.
3Ease of operation
If traditional GPU execution is used, then thread context switching is enabled, but latency increases due to frequent SRAM access
Solution Approach 1:
Burst instructions are pre-fetched and stored in a separate instruction cache before being needed. When a burst is triggered, the instructions are already available in the cache, eliminating the latency associated with fetching instructions from main memory during execution.
Solution Approach 2:
A separate sub-processor and instruction cache are introduced as intermediaries between the main processor and the execution units. This intermediary structure allows burst instructions to be executed with reduced latency by avoiding frequent accesses to the main SRAM-based register files.
Data Source
Figure 1
Figure 2
Figure 3
AI summary
A computer-implemented method of compiling a program is described. The method comprises: analysing a program to identify at least one group of instructions within the program that can be executed atomically; in response to identifying a group of instructions that can be executed atomically, extracting the group of instructions from the program to form a burst; creating a modified program by inserting an instruction into the program in place of the extracted group of instructions, wherein the instruction is configured to trigger execution of the burst; and saving the burst and the modified program separately.