GPU Caching Method for Video Data Processing

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Solution Overview

Problem

The slow read speed of global memory in graphic processing units (GPUs) and duplicated read operations for video data processing lower image processing performance, particularly in convolution techniques where multiple cores access memory inefficiently.

Innovation Solution

A caching method that groups pixels into horizontal and vertical pixel groups, mapping these groups to GPU cores using index information to store video data in cache memory, reducing duplicated reads and improving memory access efficiency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If multiple cores individually access global memory for video data, then each core can process data independently, but duplicated read operations occur and memory access efficiency deteriorates

Engineering Contradiction:
Improveindependent processing capabilityVSAvoidmemory access efficiency
Core Design Contradiction:
Adaptability or versatilityVSProductivity

Solution Approach 1:

The patent merges the memory access operations of multiple cores by introducing a cache memory that stores video data blocks shared by multiple cores. Instead of each core independently reading from global memory, cores read from the cache, combining their access needs into a single caching structure that serves multiple processors simultaneously.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The patent performs preliminary action by pre-loading video data blocks into the cache memory before the cores need them for processing. The cache stores anticipated data that multiple cores will need, so when cores require data, it is already available in the cache rather than requiring repeated global memory access.

Inventive Principle:
Principle #10Preliminary action

2Quantity of substance

If video data is read from global memory, then data can be accessed by multiple cores, but the slow read speed of global memory lowers image processing performance

Engineering Contradiction:
Improvedata accessibilityVSAvoidimage processing speed
Core Design Contradiction:
Quantity of substanceVSSpeed

Solution Approach 1:

The patent introduces cache memory as an intermediary between global memory and the multiple cores. The cache acts as a buffer that sits between the slow global memory and the fast processing cores, allowing cores to access data quickly from the cache while the cache periodically refreshes itself from global memory in the background.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent segments video data into blocks and distributes these blocks across the cache memory structure. By dividing the large video data into smaller manageable blocks that can be cached and reused, the system improves access speed while maintaining data accessibility for multiple cores.

Inventive Principle:
Principle #1Segmentation

3Productivity

If each core accesses global memory individually, then data processing can be parallelized, but duplicated read operations increase memory access time

Engineering Contradiction:
Improveparallel processing capabilityVSAvoidmemory access time
Core Design Contradiction:
ProductivityVSLoss of time

Solution Approach 1:

The patent merges redundant memory access operations by having multiple cores share a common cache memory. Instead of each core performing separate read operations from global memory, the cache consolidates these access patterns and serves multiple cores from a single cached copy of the data block, eliminating duplicated reads.

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentUS10140681B2Caching method of graphic processing unit
Publication Date: 2018.11.27 INNODEP
  • US10140681B2 patent drawing
  • US10140681B2 patent drawing
  • US10140681B2 patent drawing

AI summary

The present invention relates to a caching method of multi-core graphic processing unit (GPU) for improving image processing performance by efficiently storing video data into the cache memory out of the global memory. One aspect of the present invention is to provide a caching method of graphic processing unit (GPU) having multiple cores wherein at least a part of pixels out of A*B pixels of video data are cached into a cache memory in order to perform image processing on k pixels of N*N size (where, k, N, A and B are natural numbers; k=N*N; A>N; B>N), the method comprising: grouping the at least a part of pixels out of A*B pixels into k pixel groups; mapping the k pixel groups to k cores of the GPU one-to-one basis by utilizing index information of each of the k pixels; and storing video data of the k pixel groups in the cache memory with reference to the mapping result.