GPU Command Buffer MAC Verification for Secure Graphics Copy
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Solution Overview
Problem
Current graphics processing units (GPUs) face challenges in efficiently handling diverse operations due to limitations in programmability and parallel processing techniques, particularly in SIMT architectures, which can lead to inefficiencies in graphics and general-purpose computing tasks.
Innovation Solution
The integration of a parallel processing unit with a scheduler and processing cluster array within the GPU, utilizing SIMT and SIMD techniques, along with dedicated circuitry for command processing, enables efficient allocation and execution of graphics and general-purpose workloads, enhancing performance and flexibility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If SIMT architecture is used to maximize parallel processing, then processing throughput is improved, but thread synchronization overhead increases
Solution Approach 1:
The patent divides the processing system into multiple independent processing clusters, each capable of executing threads independently. This segmentation allows parallel processing to proceed without requiring constant synchronization between clusters, reducing synchronization overhead while maintaining high throughput.
Solution Approach 2:
The patent implements preliminary thread scheduling and resource allocation before execution begins. By pre-organizing threads and resources, the system minimizes runtime synchronization requirements, allowing SIMT parallel processing to achieve maximum throughput without excessive synchronization overhead.
2Reliability
If fixed function computational units are used, then processing reliability is improved, but operational flexibility deteriorates
Solution Approach 1:
The patent implements processing units that can operate in multiple modes - they can execute fixed-function operations for reliable graphics processing and programmable operations for flexible general-purpose computing. This multi-functionality allows the same hardware to provide both reliability and adaptability across different workloads.
Solution Approach 2:
The patent makes the computational units dynamically reconfigurable, allowing them to switch between fixed-function and programmable modes based on workload requirements. This dynamic capability enables the system to maintain reliability when fixed functions are needed while providing flexibility when programmability is required.
3Adaptability or versatility
If programmable portions are added to graphics processors, then operational flexibility is improved, but device complexity increases
Solution Approach 1:
The patent segments the programmable functionality into discrete processing clusters with standardized interfaces. This modular approach allows programmability to be added without creating monolithic complexity, as each cluster can be independently managed and configured.
Solution Approach 2:
The patent introduces a scheduler as an intermediary layer that manages the complexity of programmable operations. The scheduler handles thread management, resource allocation, and coordination, shielding the underlying hardware complexity from users while enabling flexible programmable operations.
4Speed
If pipelining techniques are implemented, then processing speed is improved, but resource management complexity increases
Solution Approach 1:
The patent implements self-service mechanisms within the pipeline stages, where each stage automatically manages its own resources and coordination with adjacent stages. This reduces the overall resource management complexity by distributing management responsibilities throughout the pipeline rather than requiring centralized control.
Data Source
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AI summary
Methods, apparatuses and system provide for technology that interleaves a plurality of verification commands with a plurality of copy commands in a command buffer, wherein each copy command includes a message authentication code (MAC) derived from a master session key, wherein one or more of the plurality of verification commands corresponds to a copy command in the plurality of copy commands, and wherein a verification command at an end of the command buffer corresponds to contents of the command buffer. The technology may also add a MAC generation command to the command buffer, wherein the MAC generation command references an address of a compute result.