Control Circuitry for Distributed GPU Work Distribution
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Solution Overview
Problem
As the number of shader cores in GPUs increases, efficiently distributing and scheduling graphics work becomes challenging, particularly in ensuring that higher-priority work is not blocked by lower-priority work in distributed architectures.
Innovation Solution
The implementation of primary control circuitry that maps logical slots to distributed hardware slots, using various distribution modes and techniques such as affinity-based scheduling, software overrides, and priority management to optimize work distribution and prevent priority inversion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If work is distributed to multiple replicated shader cores, then processing power and productivity are improved, but tracking usage and preventing blocking of high-priority work becomes more difficult
Solution Approach 1:
The patent introduces data master circuitry as an intermediary layer between the work distribution interface and replicated shader cores. This mediator tracks resource usage, manages work distribution, and prevents blocking of high-priority work by coordinating access to shared resources across multiple shader cores, thereby resolving the complexity of tracking in distributed architectures.
2Productivity
If the number of shader cores is increased, then compute capabilities are improved, but work distribution and scheduling becomes more challenging
Solution Approach 1:
The patent segments work distribution into distinct functional units: data master circuitry for tracking and coordination, replicated shader cores for parallel execution, and hierarchical resource management. This segmentation allows each component to specialize in specific tasks, making work distribution and scheduling more manageable as the number of shader cores increases.
Solution Approach 2:
The data master circuitry performs preliminary tracking and coordination of work distribution before tasks are assigned to replicated shader cores. By pre-managing resource allocation and priority scheduling at the data master level, the system simplifies the subsequent execution phase across multiple cores.
3Productivity
If distributed architecture is used, then processing capacity is improved, but blocking of high-priority work by lower-priority work occurs more frequently
Solution Approach 1:
The patent implements local quality by assigning different priority levels and resource access rights to different work types within the distributed architecture. High-priority work receives preferential treatment in resource allocation and scheduling decisions at the data master circuitry level, ensuring that critical tasks are not blocked by lower-priority operations even in a distributed environment.
Data Source
AI summary
Disclosed techniques relate to circuitry configured to aggregate and report usage information in a distributed processor (e.g., a GPU). In some embodiments, graphics processor circuitry that includes at least first and second portions that are respectively configured to execute sets of graphics work. First utilization circuitry may track execution time for sets of graphics work on the first portion of the graphics processor circuitry and second utilization circuitry may track execution time for sets of graphics work on the second portion of the graphics processor circuitry. Command queue circuitry may store multiple different command queues. Control circuitry may access the first and second utilization circuitry and aggregate utilization data on a per-command-queue basis, where for a given command queue, the aggregated utilization data indicates respective utilization of the first and second portions of the graphics processor circuitry. The control circuitry may provide the aggregated per-command-queue utilization data in software-accessible registers.