GPU Convolution Pixel Data Reorganization for Stride 2 Efficiency
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Solution Overview
Problem
Convolution operations using filters with increased stride or dilation result in increased resource usage and power consumption due to the need for more operations and shared memory access, which hampers efficiency in graphics processing units (GPUs).
Innovation Solution
The proposed solution involves reorganizing convolution pixel data with a stride of 2 or dilation of 2 into multiple smaller regions within a general-purpose register (GPR), allowing for a sliding window-based convolution scheme that reduces the number of operations and eliminates the need for shared memory access by performing convolution on each smaller region and reassembling the results.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If convolution operations use filters with increased stride or dilation, then the receptive field and coverage area increase, but resource usage and power consumption increase due to more operations and shared memory access
Solution Approach 1:
The patent divides the convolution operation into multiple smaller regions within the GPR, processing each region separately with a sliding window approach. This segmentation reduces the computational complexity and memory access requirements compared to processing the entire receptive field at once, thereby lowering power consumption while maintaining full coverage.
Solution Approach 2:
The patent reorganizes pixel data into a three-dimensional structure within the GPR (grouping pixels into quads, then into regions). This dimensional reorganization enables more efficient data access patterns and reduces shared memory access, decreasing power consumption while preserving the full receptive field coverage through systematic processing of all regions.
2Area of stationary object
If convolution operations use filters with increased stride or dilation, then the coverage area increases, but the number of operations increases leading to decreased efficiency
Solution Approach 1:
By segmenting the convolution operation into smaller regional processing tasks within the GPR, the patent enables parallel processing of multiple regions simultaneously. This approach maintains comprehensive coverage while improving computational efficiency through better resource utilization and reduced operation overhead.
Solution Approach 2:
The patent performs preliminary reorganization of pixel data into structured regions within the GPR before executing convolution operations. This pre-processing step optimizes data layout for efficient access patterns, reducing the number of operations required and improving overall computational efficiency while maintaining full coverage area.
3Ease of operation
If convolution operations access shared memory frequently, then data availability improves, but resource usage and power consumption increase
Solution Approach 1:
The patent nests multiple levels of data organization within the GPR: pixels are grouped into quads, quads into groups, and groups into regions. This nested structure enables efficient data reuse and local access patterns, reducing the need for frequent shared memory accesses while maintaining data availability throughout the processing pipeline, thereby lowering power consumption.
Solution Approach 2:
The patent creates copies of pixel data in organized regions within the GPR, allowing multiple processing operations to access the same data locally without requiring repeated reads from shared memory. This copying strategy ensures data availability for all operations while significantly reducing shared memory access frequency and associated power consumption.
4Adaptability or versatility
If convolution operations are performed on larger filter sizes, then the processing capability improves, but the complexity of data organization and memory access increases
Solution Approach 1:
The patent applies segmentation by dividing large filter operations into smaller regional processing tasks within the GPR. Each region handles a subset of the convolution computation with simplified data organization rules, making the overall system more manageable and less complex while maintaining the capability to process large effective filter sizes through cumulative results from all regions.
Data Source
AI summary
The disclosed technology generally relates to a graphics processing unit (GPU). In one aspect, a GPU includes a general purpose register (GPR) having registers, an arithmetic logic unit (ALU) configured to read pixels of an image independently of a shared memory, and a level 1 (L1) cache storing the pixels read by the ALU. The ALU can implement pixel mapping by fetching a quad of pixels, which includes pixels of first, second, third, and fourth pixel types, from the L1 cache, grouping the pixels of the different pixel types of the quad into four groups based on pixel type, and, for each group, separating the pixels included in the group into three regions that each have a set of pixels. The pixels for each group can then be loaded into the registers corresponding to the three regions.