GPU-CPU Cooperative Variable Length Data Bit Packing

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Solution Overview

Problem

In parallel computing contexts, packing variable length data for serial execution by a central processing unit is time-intensive and can be a bottleneck due to the need for efficient bit packing, which is not effectively addressed by existing methods.

Innovation Solution

A cooperative approach between a graphics processing unit (GPU) and a central processing unit (CPU) is employed, where the GPU performs parallel bit shift operations on variable length data and the CPU completes the packing with bitwise OR operations and copy operations, optimizing the packing process to achieve contiguous, gap-free data storage for serial processing.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If variable length data is packed using traditional serial processing methods, then data can be stored in contiguous memory locations, but the packing process becomes time-intensive and creates a bottleneck in system performance

Engineering Contradiction:
Improvepacking speedVSAvoidpacking time
Core Design Contradiction:
ProductivityVSLoss of time

Solution Approach 1:

The patent divides the data packing process into two distinct segments: (1) GPU performs parallel bit shift operations on variable length data to prepare it for packing, and (2) CPU performs the final packing using bitwise OR operations. This segmentation allows each processor to handle the task that best suits its architecture, with the GPU handling the computationally intensive bit manipulation in parallel and the CPU completing the packing operation.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces an intermediary data structure that stores the results of GPU bit shift operations before final packing by the CPU. This intermediary structure acts as a buffer that allows the GPU and CPU to work in parallel, with the GPU preparing data that will be subsequently packed by the CPU without creating a bottleneck, as the intermediary storage decouples the two processing stages.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Productivity

If multiple process units operate in parallel to solve computational problems, then speed and throughput improve, but the output data requires time-intensive packing for serial execution

Engineering Contradiction:
ImprovethroughputVSAvoidpacking complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent changes the parameter of data representation from variable length formats to a standardized packed format suitable for serial processing. By transforming the data parameters through bit shift operations on the GPU followed by bitwise OR packing on the CPU, the system maintains high throughput from parallel processing while converting output to a form that can be efficiently processed serially by the CPU.

Inventive Principle:
Principle #35Parameter changes

3Reliability

If variable length data is packed sequentially by the CPU, then data integrity is maintained, but processing speed decreases significantly

Engineering Contradiction:
Improvedata integrityVSAvoidprocessing speed
Core Design Contradiction:
ReliabilityVSSpeed

Solution Approach 1:

The patent applies preliminary action by having the GPU perform bit shift operations on variable length data before the CPU performs the final packing operation. This preliminary processing prepares the data in a format that simplifies the subsequent CPU packing operation, allowing the CPU to maintain data integrity through careful bitwise OR operations while the GPU handles the speed-intensive bit manipulation in parallel.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS11960887B2Graphics processing unit and central processing unit cooperative variable length data bit packing
Publication Date: 2024.04.16 INTEL CORP
  • US11960887B2 patent drawing
  • US11960887B2 patent drawing
  • US11960887B2 patent drawing

AI summary

Techniques related to packing pieces of data having variable bit lengths to serial packed data using a graphics processing unit and a central processing unit are discussed. Such techniques include executing bit shift operations for the pieces of data in parallel via execution units of the graphics processing unit and packing the bit shifted pieces of data via the central processing unit.