Parallel GPU CRC Computation for Low-Latency Error Checking

Solution Overview

Problem

Cyclic redundancy checks (CRCs) in current communication systems are time-consuming, especially with increased communication speeds, necessitating a more efficient method for error detection and correction.

Innovation Solution

Utilizing parallel computing architectures, specifically graphics processing units (GPUs), to process CRCs in parallel, breaking input data into segments and using precomputed generator segments to reduce latency and increase processing speed.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If traditional sequential processing is used for cyclic redundancy checks, then implementation simplicity is maintained, but processing speed becomes insufficient for improved communication speeds

Engineering Contradiction:

ImproveCRC processing speedVSAvoidprocessing architecture complexity

Core Design Contradiction:

SpeedVSDevice complexity

Solution Approach 1:

The patent divides input data into multiple segments and processes each segment in parallel using separate processing units. Each processing unit handles a specific data segment independently, computing partial CRC values that are then combined to produce the final CRC result. This segmentation enables simultaneous processing of multiple data portions, dramatically increasing overall processing speed while maintaining manageable complexity through modular design

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent precomputes generator segments based on the CRC polynomial before actual data processing begins. These precomputed generator segments are stored and readily available for use during parallel CRC computation. By performing this computation in advance, the system eliminates the need for complex real-time polynomial operations during data processing, simplifying the main processing path while achieving high-speed performance

Inventive Principle:

Principle #10Preliminary action

2Loss of time

If parallel processing architectures are implemented to increase processing speed, then latency is reduced, but device complexity increases

Engineering Contradiction:

ImproveCRC processing latencyVSAvoidparallel processing architecture complexity

Core Design Contradiction:

Loss of timeVSDevice complexity

Solution Approach 1:

The patent divides input data into multiple segments and processes each segment in parallel using separate processing units. Each processing unit handles a specific data segment independently, computing partial CRC values that are then combined to produce the final CRC result. This segmentation enables simultaneous processing of multiple data portions, dramatically increasing overall processing speed while maintaining manageable complexity through modular design

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent combines partial CRC results from multiple parallel processing units through a systematic combination process. The partial results, which are intermediate CRC values computed from different data segments, are merged using bitwise operations to produce the final CRC checksum. This combining step integrates the outputs of parallel operations efficiently, achieving low latency while controlling complexity through algorithmic optimization

Inventive Principle:

Principle #5Merging (Combining)

3Productivity

If more processing units are used for parallel CRC computation, then productivity increases, but device complexity and resource requirements increase

Engineering Contradiction:

Improveerror detection throughputVSAvoidnumber of processing units

Core Design Contradiction:

ProductivityVSDevice complexity

Solution Approach 1:

The patent designs processing units that can handle multiple functions: each unit processes a specific data segment, stores precomputed generator segments, and contributes to the final CRC calculation. The same hardware structure is replicated across multiple processing units, creating a universal module that performs identical operations on different data segments. This universality increases productivity through parallelism while controlling complexity by reusing the same design pattern

Inventive Principle:

Principle #6Universality (Multi-functionality)

Solution Approach 2:

The patent changes the parameter of data segment size and the number of processing units to optimize the balance between productivity and complexity. By adjusting these parameters, the system can be configured for different performance requirements and hardware capabilities. This parameter-based approach allows flexible scaling of productivity without proportionally increasing complexity, as the same architectural pattern is applied with different numerical values

Inventive Principle:

Principle #35Parameter changes

Data Source

PatentUS12609715B2Performing cyclic redundancy checks using parallel computing architectures

Publication Date: 2026.04.21 NVIDIA CORP

AI summary

Apparatuses, systems, and techniques to compute cyclic redundancy checks use a graphics processing unit (GPU) to compute cyclic redundancy checks. For example, in at least one embodiment, an input data sequence is distributed among GPU threads for parallel calculation of an overall CRC value for the input data sequence according to various novel techniques described herein.