Parallel GPU CRC Processing for High-Speed Wireless Data

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Solution Overview

Problem

Current methods for computing cyclic redundancy checks (CRCs) in wireless communications are serial and slow, which is inefficient for high-speed communication applications, particularly in mobile device networks where error detection and correction need to be performed quickly.

Innovation Solution

Implementing parallel computing architectures using graphics processing units (GPUs) to compute CRC values by processing data segments in parallel, utilizing precomputed generator segments and XOR operations to achieve faster processing times.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If serial computing methods are used to compute CRC values, then device complexity is reduced, but processing speed and productivity deteriorate

Engineering Contradiction:
ImproveCRC computation speedVSAvoidcomputing architecture complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent divides the input data into multiple segments and assigns each segment to a separate computing thread or processing unit. This segmentation enables parallel computation of CRC values across multiple data segments simultaneously, dramatically improving processing throughput while distributing the computational complexity across multiple simple processing units rather than requiring a single complex serial processor

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent transitions from one-dimensional serial processing to multi-dimensional parallel processing by utilizing multiple threads, processing units, or GPU cores that operate simultaneously on different data segments. This dimensional expansion from sequential to concurrent execution enables exponential improvements in CRC computation speed without proportionally increasing the complexity of individual processing units

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Loss of time

If serial computing methods are used to compute CRC values, then device complexity is reduced, but processing time increases

Engineering Contradiction:
ImproveCRC computation latencyVSAvoiderror detection throughput
Core Design Contradiction:
Loss of timeVSProductivity

Solution Approach 1:

The patent precomputes and stores generator polynomial values and other CRC computation parameters in lookup tables or pre-initialized memory structures. This preliminary preparation eliminates the need for complex real-time polynomial calculations during actual CRC processing, significantly reducing computation latency while maintaining high error detection throughput through simple table lookups and XOR operations

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

By dividing data into parallel segments processed simultaneously by multiple threads or processing units, the patent reduces the total processing time required to compute CRC values for large data sets. Each segment is processed independently and quickly, with results combined through simple XOR operations, thereby minimizing overall latency and maximizing error detection throughput

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS11095307B2Performing cyclic redundancy checks using parallel computing architectures
Publication Date: 2021.08.17 NVIDIA CORP
  • US11095307B2 patent drawing
  • US11095307B2 patent drawing
  • US11095307B2 patent drawing

AI summary

Apparatuses, systems, and techniques to compute cyclic redundancy checks use a graphics processing unit (GPU) to compute cyclic redundancy checks. For example, in at least one embodiment, an input data sequence is distributed among GPU threads for parallel calculation of an overall CRC value for the input data sequence according to various novel techniques described herein.