On-Chip Dense Memory Temporal Buffering in GPU Compute Engines
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current parallel graphics data processing systems face challenges in efficiently processing graphics data due to limitations in fixed function computational units and the need for increased parallel processing capabilities.
Innovation Solution
The use of a general-purpose graphics processing unit (GPU) with on-chip dense memory, coupled with host/processor cores, to accelerate graphics operations and machine-learning operations through parallel processing techniques such as SIMT architectures and pipelining.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If fixed function computational units are used for graphics data processing, then specific graphics operations can be performed, but processing versatility and adaptability are limited
Solution Approach 1:
The patent implements a unified computational unit architecture that can dynamically switch between different processing modes (rasterization, tessellation, geometry processing, fragment processing) through programmable shader execution. This allows a single computational unit to perform multiple graphics operations that traditionally required separate fixed-function units, thereby improving versatility without proportionally increasing device complexity.
2Productivity
If parallel processing techniques are implemented to increase processing capacity, then more graphics data can be processed, but system complexity increases
Solution Approach 1:
The patent divides the graphics processing system into multiple independent computational units (shader processors, raster processors, geometry processors) that can operate in parallel. Each unit is relatively simple in design but the collective system achieves high processing capacity through parallel execution of multiple threads and pipelines, managing complexity through modular segmentation.
Solution Approach 2:
The patent implements pipelining across multiple processing stages where data flows continuously through tessellation, rasterization, geometry processing, and fragment processing stages. Multiple threads are kept busy simultaneously at different pipeline stages, ensuring continuous useful action and maximizing processing capacity without requiring each individual unit to be overly complex.
3Speed
If on-chip dense memory is used for temporal buffering, then data access speed improves, but chip area increases
Solution Approach 1:
The patent implements a hierarchical memory architecture where dense memory is strategically placed locally at specific computational units that require high-speed access (such as shader processors and raster processors), while other areas use standard memory. This provides fast access where needed without uniformly increasing chip area across the entire device.
Solution Approach 2:
The patent employs a multi-level memory hierarchy with small fast on-chip buffers nested within computational units, intermediate cache memory nested at processing cluster levels, and larger off-chip memory providing bulk storage. This nested structure allows the system to achieve fast data access speeds for critical operations while managing chip area through the use of smaller local buffers rather than large uniform memory.
Data Source
AI summary
Apparatuses including general-purpose graphics processing units having on chip dense memory for temporal buffering are disclosed. In one embodiment, a graphics multiprocessor includes a plurality of compute engines to perform first computations to generate a first set of data, cache for storing data, and a high density memory that is integrated on chip with the plurality of compute engines and the cache. The high density memory to receive the first set of data, to temporarily store the first set of data, and to provide the first set of data to the cache during a first time period that is prior to a second time period when the plurality of compute engines will use the first set of data for second computations.