GPU DMA Controller Direct Data Transfer for Cloud Gaming Latency

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Solution Overview

Problem

Cloud gaming services face challenges in providing high-quality, low-latency video streaming due to increased computation requirements and latency issues in data transfer between processing systems.

Innovation Solution

A processing system architecture that includes a graphics processing unit, memory, direct memory access controller, and input/output bridge, allowing the graphics processing unit to issue data transfer instructions independently of the central processing unit, facilitating direct data transfer between processing systems through point-to-point connections via input/output bridges.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of time

If data transfer between processing systems is performed through conventional CPU-mediated methods, then system compatibility and control are maintained, but transfer latency increases and efficiency decreases

Engineering Contradiction:
Improvedata transfer latencyVSAvoiddata transfer control mechanism
Core Design Contradiction:
Loss of timeVSDevice complexity

Solution Approach 1:

The patent extracts the data transfer control function from the CPU by introducing a dedicated DMA controller. The DMA controller is configured to receive data transfer instructions directly from the GPU and autonomously control data transfer between the graphics memory and external processing systems, removing the CPU from the data transfer path and reducing latency.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent introduces an input/output bridge as an intermediary component between the data bus and the external bus. This bridge facilitates direct data transfer between processing systems by mediating the connection protocols and data formats, enabling efficient communication without CPU intervention while maintaining system compatibility.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Productivity

If multiple processing systems cooperate to execute game applications, then video quality and processing capability are improved, but data transfer latency between systems increases

Engineering Contradiction:
Improvegame application processing capabilityVSAvoidinter-system data transfer latency
Core Design Contradiction:
ProductivityVSLoss of time

Solution Approach 1:

The patent segments the processing workload across multiple independent processing systems, each with its own GPU and graphics memory. The DMA controller in each system enables autonomous data transfer to external systems, allowing parallel processing while minimizing inter-system transfer latency through direct memory access rather than CPU-mediated communication.

Inventive Principle:
Principle #1Segmentation

3Speed

If the CPU mediates all data transfer operations between processing systems, then system control and coordination are simplified, but transfer speed and efficiency are reduced

Engineering Contradiction:
Improvedata transfer speedVSAvoiddata transfer control architecture
Core Design Contradiction:
SpeedVSDevice complexity

Solution Approach 1:

The patent implements self-service data transfer by enabling the GPU to directly issue data transfer instructions to the DMA controller without CPU intervention. The DMA controller then autonomously manages the data transfer process between graphics memory and external processing systems, allowing the graphics subsystem to serve itself and eliminating CPU bottlenecks.

Inventive Principle:
Principle #25Self-service

Data Source

PatentUS10579571B2Processing system and multiprocessing system
Publication Date: 2020.03.03 SONY INTERACTIVE ENTERTAINMENT LLC
  • US10579571B2 patent drawing
  • US10579571B2 patent drawing
  • US10579571B2 patent drawing

AI summary

Disclosed herein is a processing system, including: a GPU generating a video; a memory storing data; a data bus connecting the GPU and the memory to each other; a DMA controller connected to the data bus; an input/output bridge connected to the data bus and connected to an external bus for transferring data to and from an external processing system which cooperates with the processing system; and a CPU cooperating with the GPU to share the data stored in the memory. The GPU issues a data transfer instruction of the data stored in the memory to the DMA controller without intervention of the CPU. The DMA controller controls, when the data transfer instruction is received, the input/output bridge to transfer the data stored in the memory to the external processing system.