GPU Double Precision Pipelines Load Balancing

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Solution Overview

Problem

Current graphics processing units (GPUs) face limitations in efficiently processing double precision matrix multiplication workloads due to bottlenecks in the graphics pipeline, particularly in supporting multiple double precision pipelines and load balancing across these pipelines.

Innovation Solution

The implementation of a graphics processing unit (GPU) architecture that includes multiple double precision pipelines with an execution resource for load balancing and a bypass loop optimization, along with thread arbitration and scoreboard management, enables efficient execution of double precision general matrix-matrix multiplication (DGEMM) operations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If multiple double precision pipelines are implemented to increase processing throughput, then productivity is improved, but device complexity increases due to additional resource management requirements

Engineering Contradiction:
Improvedouble precision matrix multiplication throughputVSAvoidpipeline management complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The execution resource is divided into multiple independent double precision pipelines (first DP pipeline, second DP pipeline, etc.), each capable of executing matrix multiplication operations independently. This segmentation allows parallel processing of multiple DGEMM operations simultaneously, increasing throughput while maintaining manageable complexity through modular pipeline design

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

A scoreboard management unit is introduced as an intermediary component that tracks and manages the execution status of multiple double precision pipelines. This mediator coordinates resource allocation, monitors pipeline states, and enables load balancing without requiring complex manual control logic, thus reducing overall system complexity

Inventive Principle:
Principle #24Intermediary (Mediator)

2Manufacturing precision

If fixed function computational units are used to process graphics data, then manufacturing precision is improved through optimized hardware, but adaptability deteriorates due to limited operational flexibility

Engineering Contradiction:
Improvegraphics processing optimizationVSAvoidoperational flexibility
Core Design Contradiction:
Manufacturing precisionVSAdaptability or versatility

Solution Approach 1:

The execution resource is designed with multi-functionality to handle both traditional graphics processing operations and double precision matrix multiplication workloads. The same hardware infrastructure supports various computational tasks through programmable computation units that can be configured for different operations, eliminating the need for separate dedicated hardware for each function

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The computational units utilize parameter changes in precision (single precision vs. double precision) and operational mode (graphics processing vs. matrix multiplication) to adapt to different workloads. By dynamically adjusting precision parameters and execution modes, the system maintains manufacturing precision for graphics while gaining versatility for scientific computing

Inventive Principle:
Principle #35Parameter changes

3Productivity

If pipelining is implemented to process graphics data in parallel, then productivity is improved through concurrent processing, but reliability deteriorates due to synchronization challenges

Engineering Contradiction:
Improvegraphics data processing throughputVSAvoidpipeline synchronization stability
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The scoreboard management unit implements feedback mechanisms that continuously monitor the execution status of each pipeline stage. This feedback loop detects synchronization issues, tracks dependent operations, and coordinates pipeline progression to ensure reliable execution while maintaining high throughput through parallel processing

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The system performs preliminary actions by pre-establishing dependency relationships between pipeline stages and pre-allocating resources for coordinated execution. This preparation enables smooth synchronization during runtime, preventing race conditions and ensuring reliable data flow between pipelines without compromising productivity

Inventive Principle:
Principle #10Preliminary action

4Productivity

If single instruction multiple thread architecture is used to maximize parallel processing, then productivity is improved, but device complexity increases due to thread arbitration requirements

Engineering Contradiction:
Improveparallel processing capabilityVSAvoidthread arbitration complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The execution resource is segmented into multiple independent double precision pipelines, each handling specific threads of computation. This segmentation simplifies thread arbitration by reducing the complexity of managing thread schedules within each pipeline while maintaining overall parallel processing capability through coordinated pipeline execution

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Each double precision pipeline is designed with self-service capabilities to manage its own thread execution and resource allocation. The pipelines independently track their execution status and coordinate with the scoreboard management unit, reducing the arbitration overhead and simplifying the overall thread management complexity while preserving high parallel processing productivity

Inventive Principle:
Principle #25Self-service

Data Source

PatentUS20240168764A1Supporting and load balancing multiple double precision pipelines in a graphics environment
Publication Date: 2024.05.23 INTEL CORP
  • US20240168764A1 patent drawing
  • US20240168764A1 patent drawing
  • US20240168764A1 patent drawing

AI summary

An apparatus to facilitate supporting and load balancing multiple double precision pipelines in a graphics environment is disclosed. The apparatus includes a processing core having at least one processing resource comprising: a first double precision (DP) pipeline to support double float operations, the first DP pipeline comprising a first set of floating point units (FPUs) configured in a pipelined configuration to enable new instructions to be issued to the first DP pipeline before previous instructions are complete; and a second DP pipeline to support the double float operations, wherein the second DP pipeline comprising a second set of FPUs configured in a pipelined configuration to enable new instructions to be issued to the first DP pipeline before previous instructions are complete.