GPU Downscaling Kernel Using Cache to Cut DDR Bandwidth
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Solution Overview
Problem
Existing graphics processing unit (GPU) downscaling operations involve repeated reading of input images and multiple kernel executions, leading to increased double data rate (DDR) bandwidth consumption and CPU utilization, which can be a bottleneck for low-tier chipsets.
Innovation Solution
Implement a method where a single input image is read and a kernel is called only once for multiple downscaling operations, utilizing GPU cache to store intermediate results and perform averaging operations efficiently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple kernel executions are performed for downscaling operations, then processing completeness is improved, but DDR bandwidth consumption increases
Solution Approach 1:
The patent combines multiple downscaling operations into a single kernel execution. Instead of executing separate kernels for each downscaling task, the invention merges multiple operations into one unified kernel that processes multiple input images simultaneously, thereby reducing the number of times input images are read from DDR memory and lowering bandwidth consumption.
Solution Approach 2:
The patent performs preliminary actions by pre-loading input images into GPU cache memory before the actual downscaling processing. This allows the kernel to access images from the faster cache memory during processing rather than repeatedly accessing slower DDR memory, thus reducing bandwidth consumption while maintaining processing completeness.
2Reliability
If multiple kernel executions are performed for downscaling operations, then processing completeness is improved, but CPU utilization increases
Solution Approach 1:
The patent merges multiple kernel executions into a single unified kernel execution that handles multiple downscaling operations. This reduces the number of CPU-GPU synchronization events and kernel launch overhead, thereby lowering CPU utilization while still achieving complete processing of all downscaling tasks.
Solution Approach 2:
The patent creates a universal kernel that can perform multiple downscaling operations with different parameters (input images, output images, downscaling factors) within a single execution. This multi-functional kernel eliminates the need for separate kernel executions for each downscaling task, reducing CPU overhead.
3Measurement precision
If input images are read multiple times for downscaling operations, then processing accuracy is improved, but processing efficiency deteriorates
Solution Approach 1:
The patent performs preliminary action by loading input images into GPU cache memory before processing. This allows the same image data to be accessed multiple times by the kernel during different downscaling operations without repeatedly reading from DDR memory, thus maintaining processing accuracy while significantly improving processing efficiency.
Solution Approach 2:
The patent introduces GPU cache memory as an intermediary between DDR memory and the processing kernel. The cache acts as a buffer that stores input image data, allowing the kernel to access the same data multiple times without repeated DDR memory accesses, thereby improving efficiency while maintaining accuracy.
Data Source
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AI summary
The present disclosure relates to methods and devices for graphics processing including an apparatus. In some aspects, the apparatus may determine a first input pixel area of an input image and a second input pixel area of the input image. The apparatus may also convert at least one of one or more first input pixels of a plurality of first input pixels or one or more second input pixels of a plurality of second input pixels. Additionally, the apparatus may store, in at least one cache or memory, the converted at least one of the one or more first input pixels or the one or more second input pixels. The apparatus may also configure at least one of one or more first output pixels of a plurality of first output pixels or one or more second output pixels of a plurality of second output pixels.