Parallel Design Rule Checking via GPU Space Partitioning
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Solution Overview
Problem
The increasing complexity of design rules in modern integrated circuit manufacturing leads to computational intensive design rule checking processes, which are time-consuming and inefficient, especially for large circuits and analogue, RF, and custom designs, where current methods take hours or days to verify compliance, hindering real-time feedback during design and editing.
Innovation Solution
A scalable parallel-computing method leveraging the power of modern graphics processing units (GPUs) through space partitioning and hierarchical tree data structures allows for parallel execution of design rule checking algorithms, minimizing memory transfer and optimizing memory allocation, enabling real-time verification.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional CPU-based sequential design rule checking methods are used, then design rule verification can be performed with simple architecture, but the checking process becomes extremely time-consuming and inefficient for large circuits
Solution Approach 1:
The patent divides the circuit layout into multiple discrete objects and organizes them in hierarchical tree structures, allowing the design rule checking process to be segmented into independent parallel tasks that can be executed simultaneously on GPU cores
Solution Approach 2:
The patent replaces traditional CPU-based sequential processing with GPU-based parallel processing, substituting the mechanical sequential execution model with a massively parallel computational model that achieves orders of magnitude speedup
2Manufacturing precision
If the number of design rules increases to accommodate modern fabrication technologies, then manufacturing precision improves, but the computational intensity and time required for verification increases significantly
Solution Approach 1:
The patent performs preliminary space partitioning and constructs hierarchical tree structures for all layout objects before the actual design rule checking begins, preparing the data structure in advance to enable rapid parallel querying during verification
Solution Approach 2:
The patent changes the computational parameters by transitioning from sequential CPU processing to parallel GPU processing, fundamentally altering the time complexity and execution speed of design rule verification
3Productivity
If real-time design rule checking is implemented during design and editing, then design efficiency improves, but the computational load and system requirements become extremely high
Solution Approach 1:
The patent introduces a spatial dimension to the computation by utilizing the GPU's three-dimensional parallel processing architecture, organizing layout objects in hierarchical trees that map efficiently to the GPU's computational grid
Data Source
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AI summary
Processing time of design rule checking (DRC) is identified as one of the most pressing bottlenecks during the design of circuits implemented in modern fabrication technologies that prescribe complex contextual rules for manufacturability. To address this issue, a method is disclosed that relies on space-partitioning the circuit, thus obtaining a tree-based geometrical representation of the circuit. Operations between geometries encapsulated in nodes belonging to one or multiple trees are shown to be well-suited for parallel processing. Disclosed are practical techniques that implement such operations on processors with parallel computing capabilities. Disclosed is an improved DRC method for implementing parallel processing of computing operations by effectively decoupling dependencies between different sequences of computing operations. In a more generic way, this approach may be used to implement parallel processing of time-consuming electronic design automation operations. A novel DRC method is disclosed that leverages the powerful computing capabilities of current GPUs (Graphic Processor Units). It is shown that, by space-partitioning the circuit, the DRC computation method can be described as a highly parallel formulation which benefits from the GPU parallel computing power. The invention relies on two level of parallelization. Firstly, multiple rules can be executed independently on multiple GPUs. Secondly, each rule is split into many independent simpler tasks that are executed in parallel on the same GPU. This is possible due to the hierarchical representation of the circuit. It is shown that leveraging parallel computing techniques greatly improves DRC execution times opening the road for real-time execution of DRC on GPUs. Indeed, in one embodiment the GPU implementation of a minimum-distance rule outperforms its single-processor counterpart by two orders of magnitude, achieving real-time design rule checking. Furthermore, the proposed algorithm is scalable to multiple GPUs, can handle multi-billion transistor devices and can accommodate all kind of manufacturing rules needed by the industry.