Edge Evaluation Sequencing for GPU Power Reduction
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Solution Overview
Problem
Current graphics processing units (GPUs) face inefficiencies in edge evaluation, requiring multiple edge evaluation circuits that consume more power and resources without significant performance improvements.
Innovation Solution
Implementing a graphics processing unit with two edge evaluation circuits coupled in parallel, allowing for efficient edge evaluation by sequencing edges across clock cycles, reducing the number of edge evaluators and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If multiple edge evaluation circuits are used to evaluate all edges of a primitive in parallel, then the edge evaluation speed is improved, but the hardware area and power consumption increase significantly
Solution Approach 1:
The primitive edges are segmented into two groups: primary edges (first and second edges) evaluated in the first clock cycle, and secondary edges (third and fourth edges) evaluated in the second clock cycle. This temporal segmentation allows the use of fewer edge evaluation circuits while maintaining evaluation completeness.
Solution Approach 2:
The edge evaluation is performed in periodic clock cycles rather than simultaneously. The first and second edges are evaluated in the first clock cycle, while the third and fourth edges are evaluated in the second clock cycle, creating a periodic evaluation pattern that reduces hardware requirements.
2Speed
If multiple edge evaluation circuits are used to evaluate all edges of a primitive in parallel, then the edge evaluation speed is improved, but the power consumption increases
Solution Approach 1:
The edge evaluation workload is segmented across two clock cycles, with only two edge evaluation circuits actively evaluating edges at any given time. This reduces the simultaneous power consumption compared to having all four circuits operating in parallel.
Solution Approach 2:
The edge evaluation operates in periodic clock cycles where circuits are activated only when needed. The third and fourth edges are evaluated in the second clock cycle using the same two circuits, creating a periodic activation pattern that reduces average power consumption.
3Area of stationary object
If two edge evaluation circuits are used with sequential evaluation, then the hardware area is reduced, but the edge evaluation time increases
Solution Approach 1:
The evaluation is segmented into two clock cycles, with the first cycle handling primary edges and the second cycle handling secondary edges. This segmentation allows area reduction while keeping the time increase minimal and acceptable.
Solution Approach 2:
The system dynamically switches between evaluating different edge pairs in different clock cycles. The sequencer dynamically directs the third and fourth edges to the edge evaluation circuits in the second clock cycle, optimizing the use of limited hardware resources.
4Use of energy by moving object
If two edge evaluation circuits are used with sequential evaluation, then the power consumption is reduced, but the edge evaluation time increases
Solution Approach 1:
The edge evaluation uses periodic clock cycles to activate circuits only when needed. This periodic action reduces average power consumption while the total evaluation time spans two clock cycles, representing a acceptable trade-off.
Solution Approach 2:
The system dynamically manages circuit activation based on which edges need evaluation. The sequencer dynamically controls the timing and pairing of edge evaluations, optimizing the balance between power consumption and evaluation time.
Data Source
AI summary
The edge evaluation technique, in accordance with one embodiment of the present technology, includes determining a number of edges of a given primitive to be evaluated. The technique also includes sequencing evaluation of a first edge by a first edge evaluation circuit and a second edge by a second edge evaluation circuit during a first clock cycle. The technique further includes sequencing evaluation of a third edge by the first edge evaluation circuit and a fourth edge by the second edge evaluation circuit during a second clock cycle if three or more edges are to be evaluated.