GPU FMA Hardware Reuse for Branch-Free Transcendental Emulation

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Solution Overview

Problem

Graphics Processing Units (GPUs) lack native support for high accuracy transcendental functions required by High Performance Computing (HPC) applications, leading to performance bottlenecks due to the need for software emulation and handling of special inputs, which diverge based on input values.

Innovation Solution

Reusing fused multiply-add execution unit hardware logic in GPUs to natively support get exponent, get mantissa, and scale instructions, allowing branch-free emulation of transcendental functions, thereby reducing the number of instructions and improving performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If software emulation is used to implement transcendental functions, then HPC applications can achieve high accuracy, but execution time increases and performance deteriorates

Engineering Contradiction:

Improveaccuracy of transcendental functionsVSAvoidexecution speed

Core Design Contradiction:

Measurement precisionVSProductivity

Solution Approach 1:

The patent implements hardware copying of the FMA execution unit's core computational logic to create a dedicated transcendental function emulator. This hardware copy includes replicated floating-point arithmetic logic, exponent manipulation circuits, and mantissa processing units that mirror the original FMA unit's structure, enabling parallel execution without software emulation overhead

Inventive Principle:

Principle #26Copying

Solution Approach 2:

The patent segments the transcendental function emulation into distinct hardware modules: exponent extraction units, mantissa processing units, and scale calculation units. Each module handles specific portions of the computation independently, allowing concurrent execution of multiple transcendental operations and eliminating the sequential bottlenecks of software emulation

Inventive Principle:

Principle #1Segmentation

2Reliability

If branch codes are used to handle special inputs, then input robustness is improved, but instruction count increases and execution complexity worsens

Engineering Contradiction:

Improvehandling of special inputsVSAvoidnumber of instructions

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The patent changes the operational parameters of the execution unit by implementing saturation arithmetic and implicit range checking mechanisms. Instead of using branch codes, the hardware automatically detects special inputs (NaN, infinity, zero) and clamps outputs to valid ranges through modified arithmetic logic, eliminating conditional branches while maintaining robustness

Inventive Principle:

Principle #35Parameter changes

Solution Approach 2:

The execution unit performs self-validation of input parameters through built-in range check circuits that automatically detect special values and adjust computation accordingly. The hardware monitors its own operational state and handles edge cases autonomously without requiring external branch instructions or complex control logic

Inventive Principle:

Principle #25Self-service

3Productivity

If dedicated native instructions are added for transcendental functions, then execution speed improves, but device complexity increases

Engineering Contradiction:

Improveexecution speedVSAvoidhardware logic

Core Design Contradiction:

ProductivityVSDevice complexity

Solution Approach 1:

The patent makes the FMA execution unit multi-functional by enabling it to perform both traditional fused multiply-add operations and transcendental function emulation. The same core arithmetic logic, register files, and data paths are configured to handle different operation types through instruction decoding, eliminating the need for separate dedicated hardware for each function

Inventive Principle:

Principle #6Universality (Multi-functionality)

Solution Approach 2:

The patent merges the transcendental function emulation logic with the existing FMA execution unit architecture. The hardware combines exponent extraction, mantissa processing, and scale calculation capabilities into the same physical unit that also performs standard floating-point arithmetic, sharing common resources like register files and data buses to minimize additional complexity

Inventive Principle:

Principle #5Merging (Combining)

Data Source

PatentUS12511121B2Native support for execution of get exponent, get mantisssa, and scale instructions within a graphics processing unit via reuse of fused multiply-add execution unit hardware logic

Publication Date: 2025.12.30 INTEL CORP

AI summary

Embodiments are directed to systems and methods for reuse of FMA execution unit hardware logic to provide native support for execution of get exponent, get mantissa, and/or scale instructions within a GPU. These new instructions may be used to implement branch-free emulation algorithms for mathematical functions and analytic functions (e.g., transcendental functions) by detecting and handling various special case inputs within a pre-processing stage of the FMA execution unit, which allows the main dataflow of the FMA execution unit to be bypassed for such special cases. Since special cases are handled by the FMA execution unit, library functions emulating various functions, including, but not limited to logarithm, exponential, and division operations may be implemented with significantly fewer lines of machine-level code, thereby providing improved performance for HPC applications.