GPU Fused SHA-2 Instruction for Lower Register Bandwidth
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Solution Overview
Problem
Conventional graphics processors face inefficiencies in processing cryptographic hashing algorithms like SHA-2 due to the high number of discrete instructions required, which increases register read/write bandwidth and overall throughput.
Innovation Solution
Implement a fused instruction in a graphics processing unit (GPU) to accelerate SHA-2 operations by combining multiple operations into a single instruction, optimizing register usage and improving throughput.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional discrete instructions are used to process SHA-2 operations in a graphics processor, then the operations can be performed using standard instruction sets, but the number of instructions increases register read/write bandwidth and reduces processing efficiency
Solution Approach 1:
The patent combines multiple discrete instructions (rotate/shift, Boolean function, and add operations) into a single fused instruction that executes all operations atomically in one cycle, eliminating the need for multiple separate instruction executions and their associated register access overhead
Solution Approach 2:
The fused instruction unit is designed to handle multiple cryptographic operations (SHA-256, SHA-512, and other hash algorithms) through a single instruction format, allowing the same hardware unit to perform diverse cryptographic functions without requiring separate specialized units for each operation
2Adaptability or versatility
If multiple discrete instructions are used for SHA-2 operations, then flexibility in operation sequencing is maintained, but the overall throughput of the graphics processor decreases
Solution Approach 1:
By merging multiple operations into a single atomic instruction that executes in one cycle, the patent eliminates the sequential execution overhead and register access delays that would otherwise limit throughput, while still maintaining algorithmic flexibility through support for various SHA-2 variants and cryptographic operations
3Device complexity
If discrete instructions are used for cryptographic hashing, then standard graphics processor architectures can be utilized, but the register read/write bandwidth is excessively consumed
Solution Approach 1:
The fused instruction combines multiple operations that would otherwise require separate register reads and writes into a single atomic execution unit, thereby reducing the total number of register access operations and bandwidth consumption while maintaining compatibility with standard graphics processor architectures
Data Source
AI summary
An apparatus to facilitate a fused instruction to accelerate performance of secure hash algorithm 2 (SHA-2) in a graphics environment is disclosed. The apparatus includes a processor comprising processing resources, the processing resources comprising execution circuitry to receive a fused SHA instruction identifying a length corresponding to a data size of the fused SHA instruction and a functional control identifying an operation type of the fused SHA instruction; based on decoding the fused SHA instruction, cause a sub-function identified by the length and the function control to be scheduled to an integer pipeline of the execution resource; and execute the sub-function of the fused SHA instruction in an integer pipeline of the execution circuitry, the sub-function to perform merged operations on a source operand of the fused SHA instruction, the merged operations comprising a rotate operation, a shift operation, and an xor operation.