GPU Hardware Checkpointing for AI Training Failure Recovery

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Solution Overview

Problem

Training large AI models at production scale is time-consuming due to their massive size and distributed nature, even when using highly optimized GPU clusters.

Innovation Solution

Implement hardware-assisted checkpointing during neural network training to enhance performance by utilizing graphics processing units (GPUs) with parallel processing techniques and hardware logic for efficient command execution, enabling rapid recovery from hardware failures.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If hardware-assisted checkpointing is implemented, then recovery speed from hardware failures is improved, but device complexity increases

Engineering Contradiction:
Improverecovery speedVSAvoiddevice complexity
Core Design Contradiction:
SpeedVSDevice complexity

Solution Approach 1:

The patent merges checkpointing functionality directly into the GPU hardware by integrating checkpoint data storage into the GPU's existing memory structures and combining checkpoint operations with normal training operations. This integration allows rapid recovery without requiring separate dedicated hardware components, thus improving recovery speed while limiting the increase in device complexity.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The patent implements preliminary action by continuously maintaining checkpoint data in GPU memory during normal training operations, so that when a hardware failure occurs, the recovery process can immediately retrieve and restore from the pre-prepared checkpoint data without waiting for external storage operations, thereby achieving fast recovery.

Inventive Principle:
Principle #10Preliminary action

2Reliability

If frequent checkpointing is performed, then reliability is improved, but productivity decreases

Engineering Contradiction:
ImprovereliabilityVSAvoidproductivity
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent applies partial action by selectively checkpointing only the most critical model parameters and intermediate results rather than the entire model state, and by performing checkpointing at optimized intervals based on training progress, thus maintaining reliability while minimizing the impact on training productivity.

Inventive Principle:
Principle #16Partial or excessive action

Solution Approach 2:

The patent ensures continuity of useful action by performing checkpointing operations in parallel with training computations using GPU's parallel processing capabilities, and by implementing asynchronous checkpointing that does not block the training workflow, thus maintaining both reliability and productivity.

Inventive Principle:
Principle #20Continuity of useful action

3Reliability

If large model checkpoints are stored in external memory, then reliability is improved, but loss of time increases

Engineering Contradiction:
ImprovereliabilityVSAvoidloss of time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent applies the nested doll principle by storing checkpoint data in a hierarchical memory structure where frequently accessed checkpoint data is kept in fast GPU memory, less frequently accessed data is stored in slower but larger memory, creating a nested storage system that balances reliability with access speed.

Inventive Principle:
Principle #7Nested doll (Nesting)

Solution Approach 2:

The patent introduces an intermediary mechanism by implementing a memory management unit that acts as a mediator between GPU memory and external storage, pre-loading checkpoint data into GPU memory before it is needed and managing data transfer operations to minimize the time loss associated with external memory access.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS20250291680A1Hardware assisted checkpoint to enable recovery from hardware failures
Publication Date: 2025.09.18 INTEL CORP
  • US20250291680A1 patent drawing
  • US20250291680A1 patent drawing
  • US20250291680A1 patent drawing

AI summary

Described herein is a technique to enable hardware driven checkpointing within an accelerator device without requiring explicit host software intervention to generate the checkpoint. One embodiment provides an accelerator device comprising a memory interconnect, a plurality of accelerator cores, and a scheduler coupled with the plurality of accelerator cores. The scheduler is configured to receive an checkpoint creation job to cause generation of a compressed checkpoint for a training operation executed via the plurality of accelerator cores, atomically create a compressed checkpoint for at least a portion of the training operation, and store the compressed checkpoint to checkpoint storage associated with the accelerator device.