GPU-HBM Integration Through CMOS Silicon Interposer

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Solution Overview

Problem

Current semiconductor device assemblies require an additional interface die between high bandwidth memory cubes and the interposer, increasing complexity and cost due to indirect connections.

Innovation Solution

Directly connecting a processing unit and memory devices to a silicon substrate with CMOS circuits, using back-end-of-line layers and a redistribution layer for interconnects, eliminating the need for an interface die by enabling direct communication through the substrate.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If an interface die is used between high bandwidth memory cubes and the interposer, then connectivity between memory and processing unit is enabled, but device complexity and manufacturing cost increase

Engineering Contradiction:
ImproveconnectivityVSAvoidassembly complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent extracts and eliminates the interface die from the assembly by directly connecting the high bandwidth memory cube to the interposer. The memory controller functions are integrated into the processing unit, removing the need for a separate interface die component while maintaining connectivity functionality.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent merges the memory controller functionality into the processing unit, combining what were previously separate components. This integration eliminates the need for the interface die and reduces the number of discrete components in the assembly.

Inventive Principle:
Principle #5Merging (Combining)

2Reliability

If an interface die is used between high bandwidth memory cubes and the interposer, then connectivity is enabled, but manufacturing cost increases

Engineering Contradiction:
ImproveconnectivityVSAvoidmanufacturing cost
Core Design Contradiction:
ReliabilityVSEase of manufacture

Solution Approach 1:

The interface die is extracted and removed from the bill of materials, directly reducing component costs. The integration of memory controller functions into the processing unit eliminates the need to purchase and assemble a separate interface die component.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

By merging the memory controller into the processing unit, the patent reduces the total component count and assembly steps, leading to lower manufacturing costs through simplified production processes and reduced material requirements.

Inventive Principle:
Principle #5Merging (Combining)

3Reliability

If high bandwidth memory cubes are connected indirectly through an interface die, then connectivity is achieved, but assembly process complexity increases

Engineering Contradiction:
ImproveconnectivityVSAvoidassembly process efficiency
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The interface die is removed from the assembly path, reducing the number of assembly steps. The direct connection between memory cube and interposer simplifies the assembly process and improves production efficiency.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

Instead of connecting memory to interposer through an intermediate interface die, the patent inverts the approach by enabling direct connection. This reversal of the traditional architecture simplifies the assembly process and eliminates unnecessary intermediate steps.

Inventive Principle:
Principle #13The other way round (Inversion)

Data Source

PatentUS12170275B2Graphics processing unit and high bandwidth memory integration using integrated interface and silicon interposer
Publication Date: 2024.12.17 MICRON TECHNOLOGY INC
  • US12170275B2 patent drawing
  • US12170275B2 patent drawing
  • US12170275B2 patent drawing

AI summary

A semiconductor device assembly that includes first and second semiconductor devices connected directly to a first side of a substrate and a plurality of interconnects connected to a second side of the substrate. The substrate is configured to enable the first and second semiconductor devices to communicate with each other through the substrate. The substrate may be a silicon substrate that includes complementary metal-oxide-semiconductor (CMOS) circuits. The first semiconductor device may be a processing unit and the second semiconductor device may be a memory device, which may be a high bandwidth memory device. A method of making a semiconductor device assembly includes applying CMOS processing to a silicon substrate, forming back end of line (BEOL) layers on a first side of the substrate, attaching a memory device and a processing unit directly to the BEOL layers, and forming a redistribution layer on the second side of the substrate.