Hierarchical Memory Addressing for GPU Cluster Data Access
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Solution Overview
Problem
Conventional multiple GPU systems face inefficiencies in data communication, requiring multiple copy operations and explicit programming, which wastes system resources and developer time due to the lack of a unified memory addressing scheme.
Innovation Solution
A hierarchical memory addressing method is introduced, where a unit of data is assigned a hierarchical address based on its location within a unified memory system, allowing efficient access across a GPU cluster by determining the hierarchy level and generating a partial address with a node identifier, and appending identifiers to create a unified address accessible by all GPUs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional separate address spaces for each GPU are used, then each GPU has dedicated memory access, but data communication between GPUs requires multiple copy operations through system memory
Solution Approach 1:
The patent merges separate address spaces into a unified address space where all GPUs can directly access any memory circuit in the cluster. This eliminates the need for intermediate copy operations through system memory, allowing direct peer-to-peer data transfer between GPUs and significantly improving communication efficiency while reducing system resource utilization.
Solution Approach 2:
The unified address space provides universal access permissions, allowing any GPU to access any memory circuit within the cluster. This multi-functional addressing scheme enables both local memory access and remote GPU memory access through the same address interface, eliminating the need for separate communication protocols and copy operations.
2Productivity
If multiple copy operations and temporary buffers are used for GPU data transmission, then data can be transferred between GPUs, but bandwidth and memory resources are wasted
Solution Approach 1:
The patent extracts the temporary buffer requirement from the data transfer process by enabling direct memory-to-memory access between GPUs. Data can be transferred directly from the source GPU's memory to the destination GPU's memory without requiring intermediate buffering in system memory, thereby eliminating unnecessary memory resource consumption.
Solution Approach 2:
The unified address space acts as a virtual intermediary that enables direct communication between GPUs without requiring physical intermediate buffers. By providing a common addressing namespace, the system allows memory circuits to be accessed directly by any GPU, eliminating the need for temporary storage buffers while maintaining data transfer capability.
3Productivity
If explicit programming instructions are required for each data transmission operation, then data can be transmitted between GPUs, but developer time and attention are wasted
Solution Approach 1:
The unified address space enables self-service data access where GPUs can directly access each other's memory using standard memory access instructions. Developers only need to use conventional load/store instructions with unified addresses, and the hardware automatically routes the access to the correct memory circuit, eliminating the need for explicit transmission programming and reducing development time.
4Ease of operation
If separate address spaces are used for each GPU, then local memory access is simple, but communication with other GPUs requires complex operations
Solution Approach 1:
The unified address space provides a universal access interface that works for both local and remote memory access. The same simple memory access instructions can be used to access either local memory or remote GPU memory, with the hardware automatically determining the appropriate target. This maintains ease of operation for local access while simplifying remote communication operations.
Data Source
AI summary
One embodiment of the present invention sets forth a technique for addressing data in a hierarchical graphics processing unit cluster. A hierarchical address is constructed based on the location of a storage circuit where a target unit of data resides. The hierarchical address comprises a level field indicating a hierarchical level for the unit of data and a node identifier that indicates which GPU within the GPU cluster currently stores the unit of data. The hierarchical address may further comprise one or more identifiers that indicate which storage circuit in a particular hierarchical level currently stores the unit of data. The hierarchical address is constructed and interpreted based on the level field. The technique advantageously enables programs executing within the GPU cluster to efficiently access data residing in other GPUs using the hierarchical address.