GPU Die ID Virtualization for Low-Latency Chiplet Partitioning
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Solution Overview
Problem
Existing virtualization technologies face inefficiencies in accessing hardware resources due to competitive access by virtual machines, increased access latencies, and data storage requirements for virtual-to-physical translations, particularly in systems with parallel data processing circuits like GPUs.
Innovation Solution
Implementing a parallel data processing circuit with spatial partitioning and virtual-to-physical identifier translations, offloading the host processing circuit from performing these translations by using a hypervisor to assign unique physical identifiers to subdivisions and storing mappings for direct translation by the processing circuit.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If virtualization is implemented to allow multiple virtual machines to share hardware resources, then resource utilization efficiency is improved, but access latency increases due to virtual-to-physical translations
Solution Approach 1:
The patent pre-establishes mapping relationships between virtual device identifiers and physical device identifiers before virtual machines need to access hardware resources. The host operating system pre-translates and stores the mapping between virtual GPU identifiers (VGUs) and physical GPU identifiers (PGUs), so that when virtual machines need to access GPU resources, the translation has already been completed or can be quickly retrieved, avoiding real-time translation overhead and reducing access latency.
2Ease of operation
If virtual-to-physical translations are performed by the host processing circuit, then hardware resource access is enabled, but data storage requirements and processing burden increase
Solution Approach 1:
The patent segments the translation burden by separating the virtual-to-physical translation function from the host processing circuit. Instead of having the host CPU perform all translations, the system divides the GPU into multiple virtual GPU instances (VGUs), each with its own identifier space. The translation mappings are stored in dedicated data structures (translation lookaside buffers or memory tables) that are separate from general system memory, reducing the storage burden on the host system and enabling parallel translation operations.
3Adaptability or versatility
If multiple virtual machines competitively access hardware resources, then resource sharing is achieved, but access performance deteriorates
Solution Approach 1:
The patent introduces an intermediary layer (the virtual GPU identifier translation mechanism) between multiple virtual machines and the physical GPU resources. Each virtual machine uses its own virtual GPU identifier to access resources, and the translation mechanism mediates these accesses by converting virtual identifiers to physical identifiers. This intermediary layer isolates the virtual machines from each other, allowing them to access GPU resources independently without direct competition, thereby maintaining resource sharing while preserving access performance.
Data Source
AI summary
An apparatus and method for efficiently accessing hardware resources in a virtualized environment. In various implementations, a computing system includes a first processing circuit and a second processing circuit that is a parallel data processing circuit. The second processing circuit includes multiple subdivisions, each with compute circuits, a memory subsystem, and a command processing circuit. The hypervisor running on the first processing circuit divides the second processing circuit into multiple partitions, each with a guest operating system and one or more subdivisions. A single mapping of multiple mappings includes a virtual function identifier that specifies a guest operating system, a virtual hardware resource identifier, and a corresponding physical hardware resource identifier. The hypervisor sends the mappings to at least the second processing circuit that uses the mappings to perform translations during execution of tasks. The first processing circuit does not perform translations.