GPU Instruction Throttling via Moving Average for Voltage Stability

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Solution Overview

Problem

Existing power management systems for computing devices, particularly graphics processing units (GPUs), face challenges in managing sudden surges in current draw, leading to voltage fluctuations that can harm components and increase costs due to the need for additional capacitors, which complicate and expand the system.

Innovation Solution

Implementing a method to throttle the instruction issue rate of a processor by dispatching a subset of instructions within a scheduling period, using a scheduling unit to maintain a moving average and adjust the throttling rate, thereby controlling current draw and reducing the need for excessive capacitors.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Stability of the object's composition

If decoupling capacitors are added to provide local power storage, then voltage stability is improved, but device complexity and cost increase

Engineering Contradiction:

Improvevoltage stabilityVSAvoidsystem complexity

Core Design Contradiction:

Stability of the object's compositionVSDevice complexity

Solution Approach 1:

The patent replaces the physical capacitor-based power stabilization system with a software-based instruction throttling mechanism. The scheduling unit dynamically adjusts the instruction issue rate to control current draw, eliminating the need for additional capacitors and their associated hardware complexity while maintaining voltage stability.

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

Solution Approach 2:

The patent extracts the power stabilization function from the hardware domain (capacitors) and relocates it to the software/scheduling domain. By removing the dependency on physical capacitors, the system achieves voltage stability through intelligent instruction throttling rather than hardware supplementation.

Inventive Principle:

Principle #2Taking out (Extraction)

2Reliability

If decoupling capacitors are added to handle current surges, then power reliability is improved, but manufacturing cost increases

Engineering Contradiction:

Improvepower reliabilityVSAvoidmanufacturing cost

Core Design Contradiction:

ReliabilityVSEase of manufacture

Solution Approach 1:

The patent substitutes the costly hardware solution (capacitors requiring physical space, assembly, and quality control) with a software-based throttling mechanism implemented in the scheduling unit. This eliminates manufacturing costs associated with additional components while maintaining power reliability through dynamic instruction rate control.

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

3Stability of the object's composition

If more capacitors are added to reduce voltage fluctuations, then power stability is improved, but IC package size increases

Engineering Contradiction:

Improvepower stabilityVSAvoidIC package size

Core Design Contradiction:

Stability of the object's compositionVSVolume of stationary object

Solution Approach 1:

The patent removes the physical capacitors from the IC package design, extracting the power stabilization function from the hardware architecture. This eliminates the space occupation and manufacturing complexity associated with fitting additional capacitors into the IC package while maintaining power stability through software-controlled instruction throttling.

Inventive Principle:

Principle #2Taking out (Extraction)

4Use of energy by moving object

If instruction issue rate is throttled to control current draw, then power management is improved, but processing capacity decreases

Engineering Contradiction:

Improveenergy consumptionVSAvoidprocessing capacity

Core Design Contradiction:

Use of energy by moving objectVSProductivity

Solution Approach 1:

The patent implements dynamic instruction throttling where the scheduling unit continuously adjusts the instruction issue rate based on real-time power consumption patterns and moving averages. This dynamic adjustment allows the system to optimize between power management and processing capacity, preventing surges while maintaining throughput during normal operation.

Inventive Principle:

Principle #15Dynamics

Solution Approach 2:

The patent employs a feedback mechanism where the scheduling unit monitors current draw and uses a moving average of historical data to determine appropriate throttling levels. This feedback loop ensures that power consumption is controlled while processing capacity is maintained through intelligent, data-driven decision-making rather than static limitations.

Inventive Principle:

Principle #23Feedback

Data Source

PatentUS9430242B2Throttling instruction issue rate based on updated moving average to avoid surges in DI/DT

Publication Date: 2016.08.30 NVIDIA CORP

AI summary

Systems and methods for throttling GPU execution performance to avoid surges in DI/DT. A processor includes one or more execution units coupled to a scheduling unit configured to select instructions for execution by the one or more execution units. The execution units may be connected to one or more decoupling capacitors that store power for the circuits of the execution units. The scheduling unit is configured to throttle the instruction issue rate of the execution units based on a moving average issue rate over a large number of scheduling periods. The number of instructions issued during the current scheduling period is less than or equal to a throttling rate maintained by the scheduling unit that is greater than or equal to a minimum throttling issue rate. The throttling rate is set equal to the moving average plus an offset value at the end of each scheduling period.