GPU Geometry Kick Distribution With Logical Slots and Segment Stitching
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Solution Overview
Problem
As GPUs become more powerful with increasing numbers of shader cores, existing work distribution and scheduling techniques significantly impact performance and power consumption, necessitating improved methods for distributing processing work to graphics sub-units.
Innovation Solution
The implementation of logical kickslot techniques that allow for virtualization of graphics work across multiple GPU sub-units (mGPUs), including fine-grained scheduling, start-when-ready execution, and streaming kickslot manager (S-KSM) to manage work queues and prioritize completion processing, along with techniques for pipelining and geometry kick distribution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional work distribution techniques are used in GPUs with large numbers of shader cores, then device complexity increases, but productivity and power consumption efficiency deteriorate
Solution Approach 1:
The patent segments the monolithic work distribution task into hierarchical levels: (1) primary control circuitry segments work into logical slots at a high level, and (2) distributed control circuitry in each sub-unit further segments into hardware slots. This hierarchical segmentation reduces the complexity of any single scheduling decision while maintaining overall productivity across the entire GPU system with numerous shader cores.
Solution Approach 2:
The patent introduces a new dimensional organization by grouping shader cores into multiple independent sub-units, each with its own control circuitry. This spatial dimensionality change allows parallel work distribution across sub-units, improving productivity without linearly increasing scheduling complexity at any single control point.
2Power
If more shader cores are added to increase GPU power, then compute capability increases, but work distribution overhead and power consumption increase
Solution Approach 1:
The patent introduces logical slots as an intermediary layer between software work submission and hardware execution. This intermediary abstraction allows the system to manage large numbers of shader cores without proportionally increasing software overhead, as the primary control circuitry can batch and organize work into logical slots that are then distributed to multiple sub-units, reducing per-core distribution overhead.
Solution Approach 2:
The patent creates replicated control circuitry in each sub-unit that copies the essential work distribution functionality. This allows parallel processing of work distribution decisions across multiple sub-units, reducing the overhead burden on any single controller and enabling efficient management of increased compute capability from additional shader cores.
3Productivity
If fine-grained scheduling is implemented to improve work distribution efficiency, then productivity increases, but device complexity and software overhead increase
Solution Approach 1:
The patent segments fine-grained scheduling into two hierarchical levels: logical slot scheduling at the primary control circuitry level, and hardware slot scheduling at the distributed control circuitry level. This segmentation allows fine-grained control of individual shader cores while maintaining simpler high-level work organization, achieving productivity gains without proportional increases in overall scheduling complexity.
Solution Approach 2:
The patent enables distributed control circuitry in each sub-unit to autonomously manage its own hardware slots and make local scheduling decisions. This self-service approach allows fine-grained scheduling to occur in parallel across multiple sub-units without requiring centralized coordination for every decision, improving productivity while limiting the growth of centralized scheduling complexity.
Data Source
AI summary
Disclosed techniques relate to parsing and assigning sets of geometry work to distributed hardware slots. In some embodiments, graphics control circuitry implements a plurality of logical slots. Control circuitry may assign a parse version of a set of geometry work to distributed hardware slots of one or more of the graphics processor sub-units that each implement multiple distributed hardware slots. Control circuitry may determine a number of segments for the set of geometry work based on execution of the parse version and assign determined segments to distributed hardware slots of respective graphics processor sub-units for execution. Stitch circuitry may stitch results of the segments processed by the assigned distributed hardware slots.