GPU Lane Mask Broadcasting for Lower Video Processing Power

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Solution Overview

Problem

The increasing power consumption of modern integrated circuits in computing devices leads to higher costs due to the need for more extensive cooling systems, which is a challenge across various computing platforms, including portable computers, mobile devices, desktops, and servers.

Innovation Solution

Implementing a power management system that assigns different power domains to partitions within a computing system, utilizing a graphics processing unit (GPU) for parallel data processing, and selectively disabling clock and power signals to inactive lanes based on operational states and region analysis to reduce power consumption.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If all lanes remain active to maintain processing capability, then productivity is improved, but power consumption increases

Engineering Contradiction:
Improveprocessing capabilityVSAvoidpower consumption
Core Design Contradiction:
ProductivityVSUse of energy by moving object

Solution Approach 1:

The patent implements dynamic lane activation where compute units can selectively activate or deactivate lanes based on the current computational workload and data parallelism requirements. This dynamic adjustment allows the system to optimize the balance between processing capability and power consumption in real-time, rather than maintaining a static configuration of all lanes always active.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent applies different operational states to different lanes within compute units. Instead of treating all lanes uniformly, the system can place some lanes in active state and others in inactive state based on local workload requirements, allowing selective power management at the lane level while maintaining overall processing capability where needed.

Inventive Principle:
Principle #3Local quality

2Temperature

If cooling systems are increased to handle higher power consumption, then temperature control is improved, but device complexity and cost increase

Engineering Contradiction:
Improvetemperature controlVSAvoidcooling system complexity
Core Design Contradiction:
TemperatureVSDevice complexity

Solution Approach 1:

The patent reduces power consumption at the source by deactivating lanes before they generate excessive heat, rather than relying on downstream cooling systems to manage thermal loads. This preliminary action of reducing power consumption prevents heat generation in the first place, simplifying the cooling system requirements.

Inventive Principle:
Principle #10Preliminary action

3Use of energy by moving object

If lanes are deactivated to reduce power consumption, then power consumption is reduced, but processing capability decreases

Engineering Contradiction:
Improvepower consumptionVSAvoidprocessing capability
Core Design Contradiction:
Use of energy by moving objectVSProductivity

Solution Approach 1:

The patent designs compute units with multiple lanes that can operate in different states, allowing the same hardware structure to serve multiple functions: full processing capability when all lanes are active, and reduced power consumption mode when some lanes are inactive. This multi-functionality enables the system to adapt to different workload requirements without sacrificing overall processing capability.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS12547235B2Dynamic vector lane broadcasting
Publication Date: 2026.02.10 ATI TECHNOLOGIES ULC
  • US12547235B2 patent drawing
  • US12547235B2 patent drawing
  • US12547235B2 patent drawing

AI summary

An apparatus and method for efficient power management of multiple integrated circuits. In various implementations, a computing system includes first partition and a second partition. The second partition includes video pre-processing circuitry that identifies regions of a video frame to be presented on a screen or monitor that don't change or regions that can have one or more of resolution and color accuracy be below a threshold. The first partition includes a parallel data processor with one or more compute units, each with multiple lanes of execution. Based on the identified regions, the first partition generates an execution mask indicating which lanes of the compute units are inactive. The parallel data processor copies result data from the active lanes to outputs of the inactive lanes.