Automatic Hardware Compression for GPU-to-GPU Graphics Links

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Solution Overview

Problem

Current graphics processors face challenges in efficiently processing graphics data due to limitations in parallel processing capabilities and the need for improved data transmission between multiple GPUs, leading to inefficiencies in graphics data operations.

Innovation Solution

Implementing lossless and lossy automatic hardware compression techniques in graphics-to-graphics network links using a multi-GPU computing system, which optimizes data transmission and enhances parallel processing efficiency by reducing data size without loss of information.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If graphics processors use traditional fixed function computational units, then processing specific graphics operations is efficient, but the ability to support a wider variety of operations is limited

Engineering Contradiction:
Improvesupport for various operationsVSAvoidprocessing efficiency
Core Design Contradiction:
Adaptability or versatilityVSProductivity

Solution Approach 1:

The patent implements programmable processing units that can execute multiple types of graphics operations through software control, replacing traditional fixed-function units. This allows a single processor architecture to handle diverse operations (vertex processing, fragment shading, geometry processing) by loading different instruction sets, thereby achieving versatility without sacrificing performance through dedicated hardware for each operation type.

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Productivity

If parallel processing techniques are implemented to process more graphics data simultaneously, then processing throughput increases, but data transmission requirements between GPUs increase

Engineering Contradiction:
Improveprocessing throughputVSAvoiddata transmission volume
Core Design Contradiction:
ProductivityVSQuantity of substance

Solution Approach 1:

The patent implements hardware compression at the source (first GPU) before data is transmitted to the destination GPU. By compressing graphics data in advance using algorithms like zlib or deflate, the system reduces the volume of data that needs to be transmitted across the network link, thereby decreasing bandwidth requirements and improving overall processing throughput in parallel GPU configurations.

Inventive Principle:
Principle #10Preliminary action

3Quantity of substance

If data compression is applied to reduce data size for transmission, then data transmission overhead is reduced, but information loss may occur

Engineering Contradiction:
Improvedata sizeVSAvoidinformation accuracy
Core Design Contradiction:
Quantity of substanceVSLoss of information

Solution Approach 1:

The patent implements a dynamic compression system that adapts between lossless and lossy compression modes based on the specific graphics data characteristics and application requirements. The system can switch between compression algorithms (e.g., lossless zlib for critical data, lossy perceptual compression for less sensitive data) to optimize the balance between data size reduction and information preservation, allowing flexible adjustment of compression strength according to operational needs.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS20250292355A1Lossless and lossy automatic hardware compression in graphics-to-graphics network links
Publication Date: 2025.09.18 INTEL CORP
  • US20250292355A1 patent drawing
  • US20250292355A1 patent drawing
  • US20250292355A1 patent drawing

AI summary

An apparatus to facilitate lossless and lossy automatic hardware compression in graphics-to-graphics network links is disclosed. The apparatus includes compressor/decompressor circuitry (CDC) integrated with physical layer (PHY) intellectual property (IP) hardware circuitry for a graphics processor unit (GPU)-to-GPU communication link communicably coupling a first GPU to one or more other GPUs, the CDC to: receive a data message from the first GPU, wherein the data message is in an uncompressed format; determine that a compression process is to be applied to the data message; apply the compression process to the data message to generate a compressed data message; and cause a GPU link IP hardware circuitry that comprises the PHY IP hardware circuitry to transmit the compressed data message over the GPU-to-GPU communication link.