GPU Processing Logic Verification Using Repeated Test Execution
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Solution Overview
Problem
Existing graphics processing units (GPUs) in safety-critical systems face challenges in verifying their processing logic due to the vast number of configurable permutations and parallel processing capabilities, making it difficult to design effective test tasks that utilize enough logic to ensure compliance with safety standards like ASIL B or D of ISO 26262.
Innovation Solution
A method and GPU architecture that involves processing a predefined set of instructions twice to generate matching outputs, using checksums or hashes to verify correctness without relying on predetermined expected outputs, and alternating between test and non-test phases to ensure continuous operation while verifying the GPU's functionality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If dual lockstep processors are used to verify processing logic, then reliability is improved, but device complexity and area increase
Solution Approach 1:
The patent uses a simplified copy-compare approach where test tasks are executed twice and outputs are compared using checksums or hashes. This provides verification without requiring identical dual lockstep processor architectures, reducing complexity while maintaining reliability.
Solution Approach 2:
The patent changes the verification parameter from comparing full processing outputs to comparing compact checksums or hashes of outputs. This dramatically reduces the complexity of verification while maintaining the ability to detect faults.
2Reliability
If dual lockstep processors are used to verify processing logic, then reliability is improved, but power consumption increases
Solution Approach 1:
The patent executes test tasks twice and compares outputs using checksums or hashes, providing verification without requiring continuous dual processor operation. This reduces power consumption compared to maintaining dual lockstep processors in constant operation.
Solution Approach 2:
The patent implements periodic verification by alternating between test phases (where verification occurs) and non-test phases (normal operation). This periodic approach reduces average power consumption while maintaining reliability through regular verification cycles.
3Reliability
If comprehensive test tasks are designed to utilize enough GPU logic for safety standard compliance, then reliability is improved, but device complexity and test overhead increase
Solution Approach 1:
The patent simplifies test design by using copy-compare with checksums or hashes instead of designing complex comprehensive test tasks. This approach inherently covers more logic paths while reducing the complexity of test task design and verification.
Solution Approach 2:
The patent creates universal test tasks that can verify multiple aspects of GPU logic through the copy-compare mechanism. A single test task structure can target different logic paths by varying inputs, reducing the need for multiple specialized test tasks.
4Reliability
If continuous verification is performed to ensure safety compliance, then reliability is improved, but productivity decreases
Solution Approach 1:
The patent alternates between test phases (verification) and non-test phases (normal processing). This periodic structure ensures safety compliance through regular verification while maintaining high productivity during non-test phases, resolving the contradiction between continuous verification and processing throughput.
Data Source
AI summary
A method of verifying processing logic of a graphics processing unit receives a test task including a predefined set of instructions for execution on the graphics processing unit, the predefined set of instructions being configured to perform a predetermined set of operations on the graphics processing unit when executed for predefined input data. In a test phase, the test task is processed by executing the predefined set of instructions for the predefined input data first and second times at the graphics processing unit so as to, respectively, generate first and second outputs. A fault signal is raised if the first and second outputs do not match.