Explicit Independent Mask Registers in GPU Threads
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Solution Overview
Problem
The use of a single implicit mask register in GPUs leads to increased instruction count, execution delay, and power consumption due to frequent data movement between registers when handling many condition control statements, especially in nested scenarios.
Innovation Solution
Implementing an explicit independent mask register system where each GPU hardware thread can access eight 128-bit-wide independent mask registers, allowing for explicit mask operations, reduction, and data movement between mask and general vector registers, reducing data movement and optimizing instruction execution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single implicit mask register is used to save encoding space, then the GPU instruction word encoding space is reduced, but the number of instructions increases and execution delay is prolonged due to frequent data movement between the implicit mask register and general registers
Solution Approach 1:
The patent divides the single implicit mask register into multiple independent mask registers (at least two: a first mask register and a second mask register). This segmentation allows different mask operations to be performed simultaneously on different registers, eliminating the need for frequent data movement between a single mask register and general registers, thus reducing execution delay while maintaining compact encoding space.
2Device complexity
If a single implicit mask register is used, then the encoding space is saved, but power consumption increases due to additional reading and writing operations between registers
Solution Approach 1:
By segmenting the mask functionality into multiple independent mask registers, the patent eliminates frequent read-write operations between a single mask register and general registers. Each mask register can be independently accessed and modified, significantly reducing the number of memory access operations and thereby lowering power consumption in the programmable processor kernel.
3Device complexity
If a single implicit mask register is used, then the device structure is simplified, but the processing capability for nested condition control statements is insufficient
Solution Approach 1:
The patent introduces multiple independent mask registers that can be selectively activated through mask address field encoding. This allows the system to handle nested condition control statements by assigning different mask registers to different nesting levels, enabling independent mask operations at each level without interfering with others, thus enhancing processing capability while maintaining relatively simple device structure.
Solution Approach 2:
The patent implements nested mask register usage where outer and inner condition control statements can utilize different mask registers simultaneously. The mask address field encoding mechanism allows nested access patterns where inner masks operate independently within the context of outer masks, enabling efficient handling of deeply nested conditional logic without requiring complex register allocation.
Data Source
AI summary
Provided is a mask operation method for an explicit independent mask register in a GPU. The method comprises: each GPU hardware thread being able to access respective eight 128-bit-wide independent mask registers, which are recorded as $m0-$m7. With regard to mask operation instructions of the explicit independent mask register in the GPU, each hardware thread in the GPU is able to access respective eight 128-bit-wide independent mask registers, and four groups of mask operation instructions are available for a user, and respectively realize a reduction operation, an extension operation and a logic operation on the mask register, and data movement between the mask register and a general vector register.