GPU Memory Instruction Fault Detection Using Master-Slave Request Copies
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Solution Overview
Problem
Graphics Processing Units (GPUs) face challenges in fault tolerance, particularly in preventing Silent Data Corruption (SDC) during General Purpose Computing (GPGPU) operations, where traditional fault detection mechanisms like ECC incur significant area overhead, and there is a need for a low-cost fault detection mechanism to protect both on-chip memories and logic, especially in power-efficient designs and critical market segments.
Innovation Solution
A system and method that converts slave requests to dummy operations, modifies the memory arbiter to issue N master and N slave global operations per cycle, uses slave requests for error checking, and employs parity information for error detection, allowing for error checking and replay of memory instructions to ensure data integrity across master and slave operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional fault detection mechanisms such as ECC are used, then reliability is improved, but area overhead increases significantly
Solution Approach 1:
The patent creates a slave copy of the master memory request and uses it for error detection purposes. The slave request is generated by copying the master request parameters (address, data, control signals) and routing it through a separate path to the memory arbiter, where it serves as a reference for detecting faults in the master request without requiring traditional ECC overhead.
Solution Approach 2:
The patent introduces an intermediary error detection mechanism that compares master and slave requests at the memory arbiter stage. This intermediary comparison process detects faults by identifying mismatches between the master and slave requests, providing fault detection capability without the area overhead of conventional ECC circuits.
2Reliability
If fault protection mechanisms are added to protect on-chip memories and logic, then reliability is improved, but device complexity increases
Solution Approach 1:
The system uses the existing slave request generation mechanism (which already exists for memory coalescing purposes in GPU architecture) to serve the additional function of fault detection. By making the slave request serve dual purposes - both memory coalescing and error detection - the patent avoids adding complex dedicated fault protection circuits while still achieving reliability improvement.
Solution Approach 2:
The slave memory request is designed to serve multiple functions: it acts as a reference for error detection, maintains compatibility with existing memory arbitration logic, and works with the existing master-slave SIMD processor architecture. This multi-functionality approach provides fault protection without significantly increasing device complexity.
3Reliability
If master and slave instructions are executed in lockstep with error checking, then reliability is improved, but productivity decreases due to replay mechanisms
Solution Approach 1:
The patent implements a selective replay mechanism where only memory requests that fail the error detection check are replayed, while successful requests proceed normally without delay. The error detection and replay logic operates in parallel with the main execution flow, allowing the system to rush through error-free operations while selectively handling only the faulty cases, thereby minimizing the impact on overall productivity.
Data Source
AI summary
A system and method for protecting memory instructions against faults are described. The system and method include converting the slave instructions to dummy operations, modifying memory arbiter to issue up to N master and N slave global/shared memory instructions per cycle, sending master memory requests to memory system, using slave requests for error checking, entering master requests to the GM/LM FIFO, storing slave requests in a register, and comparing the entered master requests with the stored slave requests.